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Ultra96-V2 ON Semiconductor Dual Camera Mezzanine hardware build instructions

ctammann

I'm going to borrow heavily from my colleague Tom Curran and his excellent HDL howto blog (Avnet HDL git HOWTO (Vivado 2020.1 and earlier)). I highly recommend reading through that blog before continuing. I will modify it as needed to help you build the hardware design for the 96Boards ON Semiconductor Dual Camera Mezzanine design using Ultra96-V2. I will preface this blog post by saying I have been a power and hardware designer most of my career. In an effort to diversify and help out on more projects I've decided to learn more about Xilinx tools, virtual boxes, Linux, etc. It's been a challenge to say the least, but I have to say the guys on my team have put together some incredible materials as far as guides and instructions to get you started. I have attached the install procedure I followed to setup a virtual machine with the proper tools in order to create this build. If you do not have Vivado 2020.1 installed on a Linux machine, please follow the virtual box install instructions before continuing.

 

If you've gotten through the pain of installing all the tools, hopefully our "stats" align:

 

  • Ubuntu v18.04 LTS 64-bit host OS
  • PetaLinux tools installed
  • Vivado 2020.1
  • At least 100GB of free disk space

 

A couple other notes about this build. There is an IP block inside this design that requires a v_osd IP license. This IP core license is included in the SDSoC license that ships with Ultra96-V2 so anyone working with this design should have access to it. Unfortunately if you do not have this license then you will not be able to successfully build this design. There are plans to replace this IP block, but there is no timeline in place so I would expect months not weeks. Bottom line, find your SDSoC license that came with Ultra96-V2.

 

If you need help with licensing, please refer to the attached getting started guide for Ultra96-V2. Page 30 starts the instructions on setting up your license.

 

It took quite a bit of time to convert this design over from a locally built design to work with our HDL structure on GitHub. Huge thanks to Dan Rozwood, Tom Curran and Kevin Keryk for helping me do the conversion. Now that the conversion has been done, the design can easily be rebuilt from github and future updates should not break the design as it will be maintained along with the rest of the library. Below you will find a series of commands that will build this hardware design for you from a terminal window. I have highlighted the commands that need to be entered:

 

# 
# Setup Xilinx environment 
# It is recommended to also add these lines to the end of your ~/.bashrc file 
# 
$ TOOLS_VER=2020.1 
$ source /tools/Xilinx/Vivado/$TOOLS_VER/settings64.sh 
$ source /tools/petalinuxv2020.1-final/settings.sh  

# 
# Clone the repositories 
# 

$ cd ~ 
$ mkdir -p git/avnet 
$ cd git/avnet/ 
$ git clone https://github.com/Avnet/bdf.git 
$ git clone https://github.com/Avnet/hdl.git 
$ git clone https://github.com/Avnet/petalinux.git 
$ cd bdf 
$ git checkout master 
$ cd ../petalinux 
$ git checkout 2020.1 
$ cd ../hdl 
$ git checkout 2020.1  

# 
# Run the Vivado build script for the Ultra96-V2 dualcam design 
# 

$ cd Scripts 
$ vivado -mode batch -source ./make_ultra96v2_dualcam.tcl

 

When the design is done building (keep in mind it takes a while, while in hours not minutes, note the time shown in the capture below) you will see this:

 

You can then open Vivado and navigate to the project, which should be here:

 

You can then navigate the project, connect to your target hardware and program if you'd like (be sure the boot mode is set to JTAG) or check out the block design. You're block design should look something like this:

 

You'll still need to build petalinux on top of this to have the full OOB image. When that design has been fully validated in our Github process I will post a followup blog outlining the complete build.

 

Ultra96-V2Ultra96-V2

Attachments:
Ultra96-V2-GSG-v1_1.pdfUltra96-V2-GSG-v1_1.pdf
VirtualBox_Installation_Guide_2020_1_v1p1.pdfVirtualBox_Installation_Guide_2020_1_v1p1.pdf
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Top Comments

  • in reply to bhfletcher

    Ah, I got it.  Thanks for pointing that out.  I see the error in what I posted:

    write_bitstream failed  
ERROR: [Common 17-69] Command failed: This design contains one or more cells for which bitstream generation is not permitted:  
ULTRA96V2_i/LIVE_VIDEO_DP/v_osd_0/U0 (<encrypted cellview>)  
If a new IP Core license was added, in order for the new license to be picked up, the current netlist needs to be updated by resetting and re-generating the IP output products before bitstream generation.  
ERROR: [Common 17-69] Command failed: ERROR: [Common 17-69] Command failed: This design contains one or more cells for which bitstream generation is not permitted:  
ULTRA96V2_i/LIVE_VIDEO_DP/v_osd_0/U0 (<encrypted cellview>)  
If a new IP Core license was added, in order for the new license to be picked up, the current netlist needs to be updated by resetting and re-generating the IP output products before bitstream generation.

     

    Yeah, I have the voucher and added the code to my Xilinx License account and then created a Xilinx.lic for the VM.  The build for PetaLinux seems to be going fine and I'll give this a try again once that finishes.

  • in reply to jomoenginer

    It's not the xczu3eg that is causing you problems. It is the v_osd IP license. describes this in the blog above:

    There is an IP block inside this design that requires a v_osd IP license. This IP core license is included in the SDSoC license that ships with Ultra96-V2 so anyone working with this design should have access to it. Unfortunately if you do not have this license then you will not be able to successfully build this design. There are plans to replace this IP block, but there is no timeline in place so I would expect months not weeks. Bottom line, find your SDSoC license that came with Ultra96-V2.

     

    Do you still have the SDSoC license voucher that came with your Ultra96-V2 kit? Use that to generate a license and that should solve your problem.

     

    Bryan

  • I was able to get through most of the build with this with the changes to the VM I posted in the PetaLinux post, but the build still fails for the issue below:

     

    Perhaps I need to add the license for the 'xczu3eg' to my Xilinx license manager.

     

    INFO: [Hsi 55-2053] elapsed time for repository (/tools/Xilinx/Vivado/2020.1/data/embeddedsw) loading 2 seconds
INFO: [Project 1-1042] Successfully generated hpfm file
write_project_tcl: Time (s): cpu = 00:00:18 ; elapsed = 00:00:44 . Memory (MB): peak = 4159.301 ; gain = 0.000 ; free physical = 4348 ; free virtual = 11916
Command: write_bitstream -force /home/vitis20201/git/avnet/hdl/Scripts/.Xil/Vivado-3330-vitis20201-VirtualBox/xsa/ULTRA96V2.bit
Attempting to get a license for feature 'Implementation' and/or device 'xczu3eg'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xczu3eg'
INFO: [Common 17-83] Releasing license: Implementation
91 Infos, 98 Warnings, 1 Critical Warnings and 1 Errors encountered.
write_bitstream failed
ERROR: [Common 17-69] Command failed: This design contains one or more cells for which bitstream generation is not permitted:
ULTRA96V2_i/LIVE_VIDEO_DP/v_osd_0/U0 (<encrypted cellview>)
If a new IP Core license was added, in order for the new license to be picked up, the current netlist needs to be updated by resetting and re-generating the IP output products before bitstream generation.
ERROR: [Common 17-69] Command failed: ERROR: [Common 17-69] Command failed: This design contains one or more cells for which bitstream generation is not permitted:
ULTRA96V2_i/LIVE_VIDEO_DP/v_osd_0/U0 (<encrypted cellview>)
If a new IP Core license was added, in order for the new license to be picked up, the current netlist needs to be updated by resetting and re-generating the IP output products before bitstream generation.


    while executing
"source ./ProjectScripts/$project.tcl -notrace"
    ("ULTRA96V2" arm line 2)
    invoked from within
"switch -nocase $board {
   PZ7015_FMCCC               -
   PZ7030_FMCCC               -
   PZ7010_FMC2                -
   PZ7020_FMC2                ..."
    (file "./make.tcl" line 361)

    while executing
"source ./make.tcl -notrace"
    (file "./make_ultra96v2_dualcam.tcl" line 69)
INFO: [Common 17-206] Exiting Vivado at Wed Mar 17 14:43:11 2021...

  • Note:

     

    The following line is not correct:

    $ source /tools/petalinuxv2020.1-final/settings.sh

     

    This should be:

    $ source /tools/petalinux-v2020.1-final/settings.sh

  • in reply to ctammann

    As they say, "better late than never"
    Yes, this is very useful to me. Thanks a lot for posting this. I am usually comfortable with the hardware (vivado) side of things and also baremetal/rtos software. However, i have yet to get to the same comfort level on the Petalinux integration side.
    If you know of a good resource to understand and learn about integrating a hardware component as a device in petalinux, pls do share. In the meantime, i will review the scripts on the git repositories referenced above.

    Thanks again.

     

    Best Regards,
    Saad