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  • Author Author: Jan Cumps
  • Date Created: Date Created
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Vivado: how to override generic values

Jan Cumps

In HDL languages, you can define generics. These are values that are assumed by default, but can be overridden. In VHDL, this may look like this:

ENTITY spi_master IS
  GENERIC(
    data_length : INTEGER := 16);     --data length in bits
  PORT(
    -- ...................
    tx		: IN     STD_LOGIC_VECTOR(data_length-1 DOWNTO 0);  --data to transmit
    rx	   : OUT    STD_LOGIC_VECTOR(data_length-1 DOWNTO 0)); --data received
END spi_master;

We're looking at a reusable SPI Master IP in VHDL. The data length of a SPI interface is defaulting to 16 bits. When you drop this IP on the block design, you see:
image
Both tx and rx have assumed the default 16 bit length. In my design, the SPI data length is 8 bits. In ISE, where there's no block design, I would override the default value in my VHDL code, when creating the SPI module. In Vivado, where you drop the module on the block diagram, you can override the value by selecting Customise Block (it initially shows 16, the default value from the IP's design):
image
Once done, the block design (and your design) adapts to the override:
image

Parents

  • I just had a nightmare vision of the Vivado Block design being a distant relative of Labview.

  • in reply to wolfgangfriedrich

    I see that you wrote this at 3 AM Slight smile.

    To help you get over next night:

    • you don't have to use block designs. Several Digilent examples (both VHDL and Verilog) use Vivado with HDL only, and combine all IP in HDL.
    • the purpose of the block design is not to write IPs in it. It's the place where you tie the IPs together (whether they are Xilinx proprietary, VHDL, Verilog, Vitis HLS, ...)
    • (more obvious with the Zynq): once you use complex IPs like the AXI, DMA, MicroBlaze, or the on-chip ARM where applicable, the block design approach, with config wizards, helps to make the design complexity graspable.
    • don't drink coffee after 18:00.
  • in reply to Jan Cumps

    Haha, it is always 3 AM somewhere. Not sure what happened, but I was writing this comment at ~10 pm ADT, would be 3 am in central Europe. Maybe my tablet is still in vacation mode, I was in Germany a few weeks ago.  

    So far I have only used the DHL only approach. I should check out the block design, especially for a waiting project that is going to use the SDRAM on my ARTY S7 board. At work we have some top level VHDL designs that are several thousand lines long. Once you understand them, you really understand the design.

    You can always counter too much coffee with a beer or two to make you tired.

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  • in reply to Jan Cumps

    Haha, it is always 3 AM somewhere. Not sure what happened, but I was writing this comment at ~10 pm ADT, would be 3 am in central Europe. Maybe my tablet is still in vacation mode, I was in Germany a few weeks ago.  

    So far I have only used the DHL only approach. I should check out the block design, especially for a waiting project that is going to use the SDRAM on my ARTY S7 board. At work we have some top level VHDL designs that are several thousand lines long. Once you understand them, you really understand the design.

    You can always counter too much coffee with a beer or two to make you tired.

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