Trigger pulse generation inside FPGA

Linas, if I understand correctly, you have an asynchronous pulse which you are feeding directly into 'aclr' which I guess is a synchronous block of logic. The trigger pulse amy be as short as 1ns. The first issue is that this pulse is almost certainly too short to reliably clear anyhting in the FPGA and if it is asynchronous to the ELIS_SK clock it will not reliably meet timing even if it is long enough - sometimes bad things will happen when the trigger arrives at just the wrong time relative to the clock.

I think you need to stretch your trigger pulse in hardware to be at least 1 clock cycle long. Thn you need to synchronise it to the internal FPGA clock by passing though at least 2 flip flops, then you can detect the rising or falling edges reliably and do the clearing. You will get  a delay of three clock cycles but this can't be avoided with an FPGA. It may be possible to condition the trigger pulse in some other way or to use a PLL on the FPGA to generate a faster internal clock to synch the trigger pulse .

Sorry, can't offer you any Verilog code because I use VHDL and my Verilog is too primitive to expsoe to the world.

MK

Clear is asynchronous to Counter, right now i am using 10ns pulse from DSP to clear it, and it works very well. This will work if clear pulse is picked by logic, that would clear counter, all other circuit will work without a problem, even if i have massive jitter compared to FPGA clock, which i will have.

i was using compare if ELIS_SK counted to 129, that would mean that i have all data clocked out, and i had other counter to count triggers, if it counts to 1, i will let ELIS_SK to count, when it finishes, i will count finishing edge, and if it's not 1, i will not let it count. in theory it should work , but it had glitches upon glitches. Idea was the same like shoot yourself, you should be able to do that, problem is that FPGA is so fast, when it tries to reset counter it see that counter is reseted, and stop reseting, generating 1ns pulse, and logic is not capable to latch on it

I think this might work:

wire clk;    // Master clock.
wire pulse;  // Pulse sets FF.
reg  PFF;    // Pulse storage FF: async set when "pulse" occurs,
             // sync reset when pulse goes away.
reg  pulse1, pulse2;    // Resynchronized versions of "pulse".
reg  PFF1, PFF2, PFF3;  // Resynchronized versions of PFF.
// Detect rising edge of PFF.  This clears your counter.
wire edge = PFF2 && !PFF3;

always @(posedge clk or posedge pulse)
if (pulse) PFF <= 1; else begin
    pulse1 <= pulse; pulse2 <= pulse1;        // Resynchronize pulse to clk.
    PFF1 <= PFF; PFF2 <= PFF1; PFF3 <= PFF2;  // Resynchronize PFF to clk.
    // "pulse" sets PFF asynchronously.  Hold PFF high until PFF3 is set,
    // and keep holding it until pulse goes away.
    // A short pulse sets PFF and PFF3 clears it.
    // A long pulse sets PFF but doesn't clear it until pulse2 goes away.
    PFF <= PFF && !(PFF3 && !pulse2);
end

Here's a better version.  I've changed PFF's clocked update so it only occurs when PFF3 is high, i.e., PFF was set several cycles ago.  "PFF <= PFF && !(PFF3 && !pulse2);" has a hazard if a short pulse occurs when clk rises.

wire clk;    // Master clock.
wire pulse;  // Pulse sets FF.
reg  PFF;    // Pulse storage FF: async set when "pulse" occurs,
             // sync reset when pulse goes away.
reg  pulse1, pulse2;    // Resynchronized versions of "pulse".
reg  PFF1, PFF2, PFF3;  // Resynchronized versions of PFF.
// Detect rising edge of PFF.  This clears your counter.
wire edge = PFF2 && !PFF3;

always @(posedge clk or posedge pulse)
if (pulse) PFF <= 1; else begin
    pulse1 <= pulse; pulse2 <= pulse1;        // Resynchronize pulse to clk.
    PFF1 <= PFF; PFF2 <= PFF1; PFF3 <= PFF2;  // Resynchronize PFF to clk.
    // "pulse" sets PFF asynchronously.  Hold PFF high until PFF3 is set,
    // and keep holding it until pulse goes away.
    // A short pulse sets PFF and PFF3 clears it.
    // A long pulse sets PFF but doesn't clear it until pulse2 goes away.
   // This version disables the PFF clock until PFF3, which is sync'd to clk.
    // PFF clears when pulse2 (also sync'd to clk) goes away.
    if (PFF3) PFF <= PFF && pulse2;
end

thank you, will try that soon and see how it goes.