TCAM implementations in FPGA

There's a Xilinx appnote on that subject that you can download:

http://www.xilinx.com/support/documentation/application_notes/xapp1151_Param_CAM.pdf

There's also some accompanying files (VHDL sources), but you will have to register with Xilinx to be able to download them. HTH.

Hi,

Do you have anything for Altera boards?

You'll need a big FPGA for that !!

(one with 2.3Mbytes of CAM )

Try Google - lots of references on the web.

I think you might need to think of  a better way of solving your problem.

There are app notes form Xlinx and Altera which describe their approaches to this problem but I don't think either could offer a CAM the size you are asking for.

What is the application ?

MK

Michael, what's the size of fpga for 16 entries for IPv4 addresses?

Amina - a certain etiquette applies on forums.

I've asked you a question (what's you application ?) which you haven't answered but just come back with a question you should easily be able to resolve yourself.  I'm not an Altera rep - I'm helping you out of the kindness of my heart. So you need to keep my interest to make me want to go on doing that.

So, if you answer my question, and tell me which parts of the Altera CAM application note you are having trouble with, then I'll help you some more.

MK

OK, kind man, I thought you were talking to the person who posted the original   it's for router classification of IP addresses.

I see now - that you aren't the same person - woops !

16 x 32 is much more reasonable.

www.xilinx.com/support/documentation/application.../xapp1151_Param_CAM.pdf

https://www.altera.com/en_US/pdfs/literature/an/an119.pdf

If you know which supplier you will use and which family of FPGA your best bet is to do a trial design - but you can see from the tables in the Xilinx app note  that you aren't going to need a huge FPGA.

MK

It happens   

Could you suggest me good code examples on how to implement ternary bit (don't care bit) input, since I have no idea how to use a variable which value isn't binary. Altera's documentation on this is complex, explaining clock signals, power consumption, etc. I need to see the code in order to understand functionality.

Are you actually using one of Altera's fancy FPGAs which supports the CAM  - if so then I can't help you much more because I don't use Altera parts.

On the other hand - tell me more about the application - if you just need a quick fix you can code a 16 x 32 CAM easily enough  - it's going to use 512 registers and some extra logic and won't go as fast as dedicated hardware but it's not that hard to do.

The key things you need to define are how many clock cycles, speed of the clock and the FPGA type (manufacturer and family).

MK

It is cyclone II which is not all the time accessible for my probes - particularly now. It should do all the comparing in one clock cycle.  I'm doing simulation in Quartus software. Application should have couple of input signals, for writing source and dest addresses, likewise masks, "enable" signal ofc, signaling the start and the end of ethernet frame and output signals for found/not found rule for specific address.