TCAM implementations in FPGA

Question

There is a need to implement TCAM memory in a FPGA. The size of TCAM memory is 128K entries. It supports both 72 bit and 144 bit addresses. Can anyone provide any info regarding this???

johnbeetem · Answer

Just for fun, I thought I might mention that you could do a 16x32 CAM quite nicely in Xilinx Spartan-3 or Spartan-6 using distributed dual-port RAMs as look-up tables. Basically, to identify a 32-bit number you encode eight 4-input LUTs (or six 6-input LUTs) with the 32-bit pattern you want to match and then AND their outputs. You can load the bit pattern you want to match using the second port. Spartan-6 has reconfigurable LUTs you can load serially. On Spartan-6 you can use a 6-input LUT as two 5-input LUTs if they have the same inputs. This could save some LUTs when doing a pair of CAM lines. This scheme works for a small number of entries since you need a bunch of LUTs for each entry. If you have a large number of IP subnet addresses to match, use the CAM as a cache and a PATRICIA tree for other entries.

michaelkellett · Answer

I see now - that you aren't the same person - woops ! 16 x 32 is much more reasonable. www.xilinx.com/support/documentation/application.../xapp1151_Param_ CAM .pdf https://www.altera.com/en_US/pdfs/literature/an/an119.pdf If you know which supplier you will use and which family of FPGA your best bet is to do a trial design - but you can see from the tables in the Xilinx app note that you aren't going to need a huge FPGA. MK

michaelkellett · Answer

Cyclone II is old and slow - I assume this isn't a commercial project. I'm going to make some big guesses here and tell you that you are doing it all wrong I bet the Ethernet frame doesn't get into the FPGA in one great huge 1400 byte lump but comes in bytes, or maybe 16 bit or 32 bit words. If it comes in as bytes you get 4 clock cycles, which will help. But the other thing you can do is to pipeline - so trade off latency against speed. What is the maximum rate of incoming Ethernet frames ? How fast is the clock. And stuff like that. Can you draw a block diagram of what you are trying to achieve (try not to pre-judge how you will do it.) I'm signing off for now so I won't respond until tomorrow morning. MK

mkr · Answer

There's a Xilinx appnote on that subject that you can download:

http://www.xilinx.com/support/documentation/application_notes/xapp1151_Param_CAM.pdf

There's also some accompanying files (VHDL sources), but you will have to register with Xilinx to be able to download them. HTH.

TCAM implementations in FPGA

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