Some FPGA Beginner Questions

Hi Christian,

I just saw your discussion today.  I don't check the element14 FPGA page much since activity is rare.

There's some good FPGA discussion in this thread at the Raspberry Pi group, including some other development boards.

I've done a lot of design with the Xilinx Spartan-3A.  It's a nice architecture.  For learning FPGAs, there's really no need to jump to the Spartan-6 unless you need the increased capacity for a specific project.  Although the Spartan-6 ICs cost about the same as Spartan-3A, the boards are still quite a bit more expensive.

Lattice had eval boards for their small-FPGA iCE40 series with promotional pricing of US$19 for a short time, but I think they're back to the standard US$39, so for that price you're better off spending a little more for a 200K gate Spartan-3A, e.g., the US$55 XESS XuLA-200.  I haven't tried that board myself, but the specs are attractive.

All the major FPGAs can synthesize from VHDL or Verilog.  JMO/YMMV: If you like to type and love the Ada language, go with VHDL.  If you like C and prefer more concise notations, go with Verilog.  My preference of the two is Verilog, but neither is really a good fit for FPGA design.  According to my recollection, VHDL was conceived for specifying and simulating behavior of VLSI designs.  Verilog was conceived for generating test vectors and expected behavior.  Neither was conceived as a language for synthesizing logic, so you have to be inventive to get the synthesizer to produce the logic you really want.  The best language I've used for that was Altera's AHDL, but I don't think it's an option any more.

FPGAs are very powerful and a lot of fun.  You get to design digital chips with zero cost for making logic errors.  Have lots of fun and please report problems and progress.

Hi John,

thanks for your info as well!

I don't check the element14 FPGA page much since activity is rare.

That's good to know. Might I ask which page is a good alternative with some more activity? So far I'v only seen another german site and it's sister over @ http://embdev.net .

Right now I pretty much narrowd down my choice to two of the Digilent boards, the Nexys 3 and the Atlys. My final considerations are:

• I'm not really interested in video processing, so the Atlys' HDMI ports don't do anything for me.
• The Atyls seems quite a lot beefier. Do I need that? Probably not. Do I want it? Absolutely
• The Nexys 3 comes with four pmod extension slots for all kinds of stuff. I don't really have a plan to use more than one but I like to have them as it seems a very nice way to add stuff to the board further down the line. The Atyls only has one pmod slot.
• I will probably get the display vmod for christmas, which is awesome   It also means that I don't really care about the VGA and HDMI ports for video output, I'll just use the small FPGA screen and be amazed by that

So in short: the nand2tetris project can be seen to run on a Cyclone II, so a Spartan 6 should be able to handle it. I would very much like to own a powerful Atyls board, but when I'm honest with myself, I probably won't need its power anyway - even if I extend the project to more stuff. In a perfect world I'd like to have a small OS running on the FPGA, and the Spartan 6 board should be able to handle that (plus, there's quite a road ahead till that milestone will be reached).

YourVerilog/VHDL perspective is very welcome! I'm just now toying around with Xilinx' ISE to get a small Hello World to run and the Verilog/VHDL question is indeed what I have to figure out next. I already started with VHDL but now I guess I'll just try a few simple logic stuff with Verilog as well.

Cheers!

Even better. I can drive to Mouser in about 10 minutes from where I live.  And the price is better than Newark.

I thought I looked there and didn't find it.

So, I would assume I have to wire up buttons and displays myself, and invent my own tutorials?  Because those other boards have IO components already built in, which was an attraction to me. 

For PLDs I started with this:

Atmel PLD 16V8, 22V10 and 20V8 PLD Trainer and USB Programmer

It had the software, device, and tutorial book, which was nice.

Not a big deal if there isn't any of that stuff, but at least I know what to expect.

-Scott

Hello Scott,

It has some nice things on board:

• LatticeXP2 FPGA: LFXP2-5E-6TN144C
• 2 Mbit SPI Flash Memory
• 1 Mbit SRAM
• On-board USB controller for JTAG programming (FTDI - FT2232H)
• 2x20 and 2x5 Expansion Headers
• Push-buttons for general purpose I/O and reset
• 4-bit DIP switch for user-defined inputs
• Eight status LEDs for user-defined outputs

see this page:

XP2 Brevia2 Dev Kit - Lattice Semiconductor

MK

Okay, I hate to beat this to a pulp,  The last thing I am looking for is where is the programming tool to download.  So far, I haven't been able to find a name, or a link to the development tools for this one. And the link in the doc is broken (on page 2).  Takes be off into some weird place....

  ISE, as scary as it is, at least I found it.

The reason is because I was burned before...  I bought the OSR  USB-FX2 demo board to learn writing device drivers for USB.  The result was I have a board that there is no support for...  They don't tell you anything about, nor give you any clue on programming the embedded device, and they don't offer support for the Windows device driver side either, claiming they want to only support the new WDF architecture (no the demo that came with the Driver Dev Kit),   So I was stuck with an expensive board that uses a micro controller, which I could only run their silly little demo code because I couldn't reprogram it, nor see how the client side functioned.

I ended up taking another path the learn that material.

And the OSR group has a lot of arrogant people in it.  (Some helpful, some not).  So asking turned into an exercise in getting abused.

You guys have been a lot more helpful :-)

-Scott

Go to this page:

Licensing - Lattice Semiconductor

and request the free license. (Paid for licenses take  a day or two to arrive, a free one may be more automatic. You may need to register some personal details (this is inevitable because although Lattice are keen to sell chips they use third party software components from companies who need to keep track of where it's used because that's all they make.)

Then go here

http://www.latticesemi.com/en/Products/DesignSoftwareAndIP/FPGAandLDS/LatticeDiamond.aspx#_229A1F76B8DF4E0098F41B8CC7935…

and download and install Diamond.

It installs a complete development environment which includes the download tools.

MK

Hi guys...

I hope I don't offend anyone, but I went ahead with the TERASIC board.  And downloaded Quartus II.

Good thing, because the version on the CD crashes when installing on my Win 7 x64.

Anyway, thanks for the reading recommendation.  Free Range VHDL is perfect for me as a programmer.  And I've been creating those demos, plus creating my own stuff as learn.

Questions:

I'm trying to understand the whole "process" statement concept.

I see that a collection of statements run concurrently, and I assume the same applies for a process.  Off the top of my head:

architecture....

Q1 <= A and B;

Q2 <= C or D;

yada : process (Z,Y) is

      Q3 => Z and Y and W; -- (yeah, I added an extra, non sensitive input)

end process yada;

Q4 <= F or G or A1;

end;

So, every one of these runs concurrently  Q1, Q2, Q3 (only if Z and Y change, but W is ignored), and Q4

But what about inside the process?   Does the process statement only mean that it uses sensitivity?

What if there was a Q3 and a Q3B inside the process?  Would they be sequential, or also concurrent?

Next question:

What about the clock?  I created a simple DFF, and used the clock by tying a defined port named CLK to the clock input pin.  All works.  It was just treating the clock input like any other input.

But is "clock" (or "CLK" or anything) actually intrinsic to the device?  Or is it just a pin...?

That is, is the only way to obtain a clock to actually define the input pin (any pin) to be where the clock input is?

If "yes", that would imply that you could tie the clock oscillator to just any old pin.

But it seems the device is intelligent enough to load from some EEPROM or flash (I haven't gotten that far in these tutorials), and that would imply the clock is needed to execute the load, and therefore the clock would have to be tied to a known and defined pin.

Thanks for any help!

-Scott

Scott Weber wrote:

 

Next question:

What about the clock?  I created a simple DFF, and used the clock by tying a defined port named CLK to the clock input pin.  All works.  It was just treating the clock input like any other input.

But is "clock" (or "CLK" or anything) actually intrinsic to the device?  Or is it just a pin...?

That is, is the only way to obtain a clock to actually define the input pin (any pin) to be where the clock input is?

If "yes", that would imply that you could tie the clock oscillator to just any old pin.

I can't help with your VHDL questions, but let me take a stab at the "clock" question.  I assume the Terasic board you mention is the DE0 board you linked to upstream.  From looking at the photo of the board, there's an oscillator Y1 that's near one of the Cyclone III pins.  So basically you assign your signal "CLK" to the FPGA pin connected to Y1.  With most FPGA design systems you can either assign pins using a textual "user constraints file" or use a GUI tool to do the assignments.  You can find pin numbers in the DE0 board's schematic.

Oscillator Y1 is probably really fast so if you want to make a counter or something that changes states slowly enough to watch, you'll need to include logic that divides the high-frequency clock down to a few Hz.  There are lots of examples of such circuits out there.

More on the clocks:

As far as VHDL is concerned a clock is a signal or input just like any other.

Almost all FPGAs have special clock input pins that can drive low skew clock distribution directly  - it is likely that the clock chip on your board is connected to such a pin and as John says there will be some way in the tools to define the IO standards it uses and to lock the physical pin the the IO named in VHDL.

If I get some time later today I'll post a complete LED blinker in VHDL - which will explain some of the key concepts re. processes and their most common use in synchronous FPGA design.

MK..

Thanks, but let me level set my experiences. 

I have been programming PC's in C and C++ for a few decades, and done a lot of stuff with micro controllers (Microchip PIC series).  Which has included computing baud rates from CPU clock sources. I also studied electrical engineering.  I wouldn't dream of creating a counter for visible display without a lot of clock dividing.

The PLD stuff I played with doesn't have a defined clock.  I could use any input as a clock, and make state machines with it.

So, that was where my question came from: does an FPGA have a need for a specific clock like a MCU does, or is the clock kind of nebulous, like that way I could assign any PLD pin to the clock (obviously not on my demo board, as it has the clock tied to several pins and I don't feel like trying to cut traces on it )

Obviously, I've already gotten the unit to run some basic decoder stuff, hex->7 seg display (like an TTL 7447).  That code didn't need a clock.  But would the FPGA have run that code, if I yanked the oscillator off the board    I'd rather ask around, then actually try it LOL.

-Scott

Scott Weber wrote:

 

So, that was where my question came from: does an FPGA have a need for a specific clock like a MCU does, or is the clock kind of nebulous, like that way I could assign any PLD pin to the clock (obviously not on my demo board, as it has the clock tied to several pins and I don't feel like trying to cut traces on it )

FPGAs have various routing resources, such as local wire segments between nearby logic elements (LEs) and longer wire segments for logic that's not nearby.  A net may have many segments connected by transistor switches.  If an LE's output fans out to many other LE inputs, the signal arrives at different inputs at different times.  This is fine for data signals, but is a disaster for clocking because you could have race conditions where a changing data signal arrives as a clock is changing, causing unpredictable behavior.

FPGAs usually have a small number of global nets for distributing clocks.  These are designed carefully at the chip level so that the signal for a net arrives at all destinations at the same time.  In Xilinx FPGAs, only certain pins can connect to global nets directly.  An external oscillator is usually connected to one of these "global clock" pins.  ("Global clock" pins can also used as ordinary I/O pins.)  The global nets can also be driven by PLLs and other FPGA clocking resources, and special clock multiplexers for implementing gated clocks cleanly.

You can also clock a register using a regular net, but if you clock two registers with the same net you'll get more skew than a global net and the design tool will give you lots of scary warnings, or may even refuse to process your design until you confirm that you really what to do this silly thing.

When the synthesis and fitter tools have finished they produce lots of reports which you should have a look at. You'll find that if you didn't use a clock in your design then there won't be a pin assigned to one, so to answer your question,

An FPGA design which consists entirely of combinatorial logic will not need a clock.

In reality such designs are very rare indeed, all FPGA's from A,L M and X are intended to implement synchronous designs so clocks (often several different ones) are needed.

For example, if you had an 8 digit 7 seg display to drive you could do it with 8 hex -> 7 seg decoders but it would almost certainly be more efficient to use 1 and share it, which would require some clocking.

As soon as you get on to anything serious you need state machines and they will need clocks.

(This is because of the way FPGAs work - I think (but can't quote a proof) that any time dependent logic design can be implemented synchronously or asynchronously from a logical point of view - it's just that FPGAs don't do asynchronous stuff well.)

I haven't forgotten the example - it may happen today.

MK

When the synthesis and fitter tools have finished they produce lots of reports which you should have a look at. You'll find that if you didn't use a clock in your design then there won't be a pin assigned to one, so to answer your question,

An FPGA design which consists entirely of combinatorial logic will not need a clock.

In reality such designs are very rare indeed, all FPGA's from A,L M and X are intended to implement synchronous designs so clocks (often several different ones) are needed.

For example, if you had an 8 digit 7 seg display to drive you could do it with 8 hex -> 7 seg decoders but it would almost certainly be more efficient to use 1 and share it, which would require some clocking.

As soon as you get on to anything serious you need state machines and they will need clocks.

(This is because of the way FPGAs work - I think (but can't quote a proof) that any time dependent logic design can be implemented synchronously or asynchronously from a logical point of view - it's just that FPGAs don't do asynchronous stuff well.)

I haven't forgotten the example - it may happen today.

MK

A simple counter example for LED twinkles !

There must be a way to add a text file - someone please tell how !

MK

Thanks.  Now I'm clear on how the clocks are used, and why there are preferred pins.

On this forum, I'm looking through the "advanced editor", and don't see any attachment options, except for video and images.  I guess they expect that you just have to copy/paste it in.

Found it....  On bottom.  On the lower right side, is "attach".  I saw it just before I hit "Add Reply".

Why it's not up in the menu bar with everything else...? No idea.

-Scott

Hello Scott,

I've never used the advanced editor before - just for a lark I'll attach a file of the same example.

Thanks.

MK

Michael Kellett wrote:

 

(This is because of the way FPGAs work - I think (but can't quote a proof) that any time dependent logic design can be implemented synchronously or asynchronously from a logical point of view - it's just that FPGAs don't do asynchronous stuff well.)

Asynchronous design is a nightmare.  It's all hazards and races.  It's important for all digital engineers to have studied asynchronous design, because it's the theory that backs up why it's so critical to meet setup, hold, and minimum clock pulse width requirements.

Asynchronous theory normally requires that logic operates in "fundamental mode".  In fundamental mode, only one input changes at a time, and the effects of that change must settle before the next input change.  If two inputs change at the same time (e.g., the clock and data inputs of a flip-flop) or one changes before the effects of the other have settled, you can have unpredictable behavior including metastability.

Asynchronous theory is tractable if you stick with fundamental mode.  If you can't assume fundamental mode, it becomes very difficult in general.

Synchronous design is a special case of asynchronous design.  In synchronous design, data signals propagate through combinational logic (with no loops) and they can change simultaneously as long as the effects settle before the next clock edge.  When the clock edge occurs, you normally assume that all registers driven by that clock update simultaneously, i.e., the changed outputs of those registers do not propagate so fast that they change inputs to registers that haven't finished updating.  As long as you use global clock nets, this requirement is satisfied by the FPGA circuits and you don't need to worry about it.

I've kept things simple by assuming edge-triggered registers with a single clock.  Using latches and multiple clocks gets a lot more interesting