Some FPGA Beginner Questions

hey dear...Greeting of the Day!!!!!

I am beginner of FPGA and VHDLl coding,I'm using spartan6(lx9,tqg144) development board i want to display text and images on monitor display by VGA connector is is possible with spartan6???!! IS, IS POSSIBLE to dispay any text ?? any image?? on monitor.

Small help also would be great helpful

thanks!!

Here are some VGA 'blogs at Gadget Factory, the maker of the Papilio Spartan-3E and Spartan-6 FPGA boards: http://www.gadgetfactory.net/tag/vga/

hey john Thanks allot !

Thanks for your warm welcome and support ..

since 11days i have been reading different tutorials and materials but

i am not satisfied how to display text and how to display image but up

to now i think i will be possible...

last question i am using spartan 6(XC6SLX9-TQG144) (xilinx X-SP6-X9)

board (it is not micro board) and i cant find its proper

configurations as well as all functions i have google it hundrads of

times but i got all information about micro board so how can i get

proper configuration..

thank you very much for your reply..

narendra rathod wrote:

 

last question i am using spartan 6(XC6SLX9-TQG144) (xilinx X-SP6-X9)

board (it is not micro board) and i cant find its proper

configurations as well as all functions i have google it hundrads of

times but i got all information about micro board so how can i get

proper configuration..

Can you tell who manufactures the board and get a part number?  I couldn't find "X-SP6-X9" either.  You might want to post an image to see if someone here recognizes it.

This is the board i am using..and the below link contain it's sellers detail

http://artofcircuits.com/product/spartan-6-fpga-development-board-xc6slx9-tqg144

So I guess it didn't come with a user manual or a schematic?  That's pretty annoying.  You might ask the vendor if either of those is available -- maybe they forgot to include a link with the board.

The board does seem to be "self-documenting" to a certain extent.  (I followed the artofcircuits.com link to get higher resolution photo.) There's a bunch of tables on the silkscreen showing which functions are attached to which FPGA pins.  For example, diodes D3 - D14 are connected to FPGA pins P33, P34, P35, etc.  So you can use these pin numbers in a User Contraint File (.ucf) to assign your signal names to functions on the board.  You'll need to play around a little to see whether the diodes are active-high or active-low.

Some of the tables are misleading.  For example, the LED digits are called "Nixie Tube", I guess out of nostalgia.  The LED segments are numbered A-G, plus DP for Decimal Point.  I would guess that BIT0-BIT7 really mean Digit 0 - Digit 7.  The BIT0-BIT7 FPGA pins probably drive transistors Q50-Q57 to turn on the digits.  I have a 'blog describing using a LOGI-Bone, LOGI-Pi, and LOGI-EDU to display a BCD counter using 7-segment displays that might be a useful reference: http://www.element14.com/community/groups/fpga-group/blog/2014/10/12/seven-segment-bcd-counter-using-the-valentfx-logi-edu

It looks like the routing is mostly on the top layer, so you can see how FPGA pins route to other components.  The Xilinx Spartan-6 data sheet shows how the FPGA pins are numbered.

It looks like you need a separate JTAG programmer with 10-pin cable to program the FPGA.  Xilinx brand programmers are pretty expensive, but there are low-cost FTDI FT2232H or FT232H modules that can do the job.  I don't know what would be available in Pakistan.

Thank you very much john..now i can understand this board some how ...there is no user guide or manual is included with this board ...i am doing the project you suggested ..but if any help about keyboard key press and display on VGA monitor it will be very helpful for my project thanks a lot..!!

For VGA, I'd start with Wikipedia which gives a good overview: https://en.wikipedia.org/wiki/Video_Graphics_Array

Since you only have three FPGA outputs for Red, Green, and Blue, you'll only be able to do 8 colors without modifying the board.  Start with something really simple like vertical color bands, and then expand to something more interesting like checker board.  At some point you can use Xilinx Block RAMs to make a character generator.

Your board should be able to interface with a PS/2 keyboard.  WIkipedia has a good overview https://en.wikipedia.org/wiki/PS/2_port and a link to a site with more details: http://www.computer-engineering.org/ps2protocol/

According to the detailed site, PS/2 has open-collector (or open-drain) I/Os, which is good because Spartan-6 has 3.3V maximum I/Os.  They're not 5V tolerant and need to be protected from external 5V signals.  I expect a PS/2 keyboard will work with 3.3V pull-ups instead of 5V pull-ups, but I'd try checking it off line just be be sure before risking damage to the Spartan-6.  It's probably been done before, so see if there are already successful projects out there.

yes that's an important thing. i read it .. honestly i understand that keyboard ps/2 has one input(clock in) and one inout(i.e data)  and VGA has one input(clock 50mhz ) and  has  five outputs (i.e. red,green,blue,horizontal sync and vertical sync)  .i am using xilinx 13.1 ISE if i want to display keyboard on vga should i have to include files like vga_controller, vga_selector ,keyboard scancodes , keyboard interfacing program with project???? should  i attach ucf filse for individuals one(i.e for vga_controller,Vga selector,keyboard )??? i am confused..

For displaying an image is it convert in .coe file and then attach with project??? i read somewhere..

XIlinx ISE has a pretty steep learning curve for a new user.  I would strongly suggest you start with some simple examples, such as controlling LEDs using push-button inputs.  Then move on to more interesting examples such as a binary counter that displays its values in the LEDs.  I did this as a demo project for the LOGI-Pi and LOGI-Bone FPGA boards.  Take a look at Experiment 2 in  http://www.element14.com/community/groups/fpga-group/blog/2014/10/03/first-experiences-with-the-valentfx-logi-bone.  The 'blog includes Verilog source code and a UCF that assigns top-level module I/Os to FPGA pins.

Once you're familiar with ISE using simple examples, then start playing with VGA.  If you do a binary counter as an example, you can then adapt it for VGA's horizontal and vertical counters.

XIlinx ISE has a pretty steep learning curve for a new user.  I would strongly suggest you start with some simple examples, such as controlling LEDs using push-button inputs.  Then move on to more interesting examples such as a binary counter that displays its values in the LEDs.  I did this as a demo project for the LOGI-Pi and LOGI-Bone FPGA boards.  Take a look at Experiment 2 in  http://www.element14.com/community/groups/fpga-group/blog/2014/10/03/first-experiences-with-the-valentfx-logi-bone.  The 'blog includes Verilog source code and a UCF that assigns top-level module I/Os to FPGA pins.

Once you're familiar with ISE using simple examples, then start playing with VGA.  If you do a binary counter as an example, you can then adapt it for VGA's horizontal and vertical counters.

Okay john as you say...but which language you suggest that i should learn verilog or vhdl up to now i read and learnt vhdl.!!

You can use VHDL perfectly well with the Xilinx, Altera, Lattice or Micro-Semi free tools.

John uses Verilog and I use VHDL so you can ask one of us if you get stuck whichever language you use.

John's suggested approach to learning is good advice.

It's easy to find lots of simple examples on the web but the important thing is to actually implement them on your hardware.  Don't forget to use the simulator before you try the code on an actual chip - you can learn a great deal by simulating !

MK

Thank you very much Micheal and John l!!

I  am starting to learn basic exampls with this website .      http://www.fpgacenter.com/examples/index.php.......but displaying text and image on vga is my project so it has time deadline it's my first project so please if you have any help regarding that also please tell me..thanks

naren.

I only had a very quick look at this site but I strongly recommend that you find another - why - because its examples use deprecated and non standard libraries which will cause you trouble in the end.

(They use IEEE.STD_LOGIC_ARITH.ALL; which is not really a standard at all, despite the name, you should use numeric_std - see here for why http://vhdlguru.blogspot.co.uk/2010/03/why-library-numericstd-is-preferred.html

Have a look here:

https://www.doulos.com/knowhow/vhdl_designers_guide/

much better.

Lattice, Xilinx and Altera have lots of examples.

MK

okay than ....how to generate block memory or BROM?? i am at half of the way but now i don't know what to do.. i am giving some snap shot below

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using

-- arithmetic functions with Signed or Unsigned values

use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating

-- any Xilinx primitives in this code.

library UNISIM;

use UNISIM.VComponents.all;

entity pong_textf is

    Port ( clk : in  STD_LOGIC;

           reset : in  STD_LOGIC;

           pixel_x : in  STD_LOGIC_VECTOR (9 downto 0);

           pixel_y : in  STD_LOGIC_VECTOR (9 downto 0);

           dig_0 : in  STD_LOGIC_VECTOR (3 downto 0);

           dig_1 : in  STD_LOGIC_VECTOR (3 downto 0);

           ball : in  STD_LOGIC_VECTOR (1 downto 0);

           text_on : out  STD_LOGIC_VECTOR (3 downto 0);

           text_r : out  STD_LOGIC;

           text_g : out  STD_LOGIC;

           text_b : out  STD_LOGIC);

end pong_textf;

architecture Behavioral of pong_textf is

signal pix_x,pix_y: unsigned(9 downto 0);

signal rom_addr: std_logic_vector(10 downto 0);

signal char_addr,char_addr_s,char_addr_l,char_addr_r,

        char_addr_o: std_logic_vector(6 downto 0);

signal row_addr,row_addr_s,row_addr_l,row_addr_r,

        row_addr_o: std_logic_vector(3 downto 0);

signal bit_addr,bit_addr_s,bit_addr_l,bit_addr_r,

        bit_addr_o: std_logic_vector(2 downto 0);

signal font_word: std_logic_vector(7 downto 0);

signal font_bit: std_logic;

signal score_on,logo_on,rule_on,over_on: std_logic;

signal rule_rom_addr: unsigned(5 downto 0);

type rule_rom_type is array(0 to 63) of std_logic_vector(6 downto 0);

--rule text Rom defination

constant RULE_ROM: rule_rom_type :=(

--row1

"1010011",--S

"1010000",--P

"1000101",--E

"1010010",--R

"1010010",--R

"1001111",--O

"1010111",--W

"1010011",--S

"1001111",--O

"1000110",--F

"1010100",--T

"1010100",--T

"1000101",--E

"1000011",--C

"1001000",--H

"0000000"

);

begin

pix_x<= unsigned(pixel_x);

pix_y<= unsigned(pixel_y);

--instantiate font ROM

font_unit: entity work.font_rom

port map(clk=>clk, addr=>rom_addr,data=>font_word);

------------------------------------------------------

--score region

--display score and ball at top

--text: "score: dd ball:d"

--scale to 16-by32 font

--------------------------------------------------------

score_on<=

'1' when pix_y(9 downto 5)=0 and

pix_x(9 downto 4)<16 else

'0';

row_addr_s<=std_logic_vector(pix_y(4 downto 1));

bit_addr_s<=std_logic_vector(pix_x(3 downto 1));

with pix_x(7 downto 4) select

char_addr_s<=

"1010011" when "0000",--S

"1010000"when "0001",--P

"1010010" when "0010",--P

"1010111" when  others;--w

----------------------------------------------------------

--logo region:

--display sprw

--used as a background

--scale to 64 by 128 font

------------------------------------------------------------

logo_on<=

'1' when pix_y(9 downto 7)=2 and

(3<= pix_x(9 downto 6) and pix_x(9 downto 6)<=6) else

'0';

row_addr_l<= std_logic_vector(pix_y(6 downto 3));

bit_addr_l<=std_logic_vector(pix_x(5 downto 3));

with pix_x(8 downto 6) select

char_addr_l<=

"1010011" when "011",--s

"1010000" when "100",--p

"1010010" when "101",--r

"1001000" when others;--w

----------------------------------------------------------------

--rule region

--------------------------------------------------------------

rule_on<= '1' when pix_x(9 downto 7)="010" and

                         pix_y(9 downto 6)="0010" else

                         '0';

                         row_addr_r<= std_logic_vector(pix_y(3 downto 0));

                         bit_addr_r<= std_logic_vector(pix_x(2 downto 0));

                         rule_rom_addr<=pix_y(5 downto 4) & pix_x(6 downto 3);

                         char_addr_r<=RULE_ROM(to_integer(rule_rom_addr));

------------------------------------------------------------------------------------

--game region

                         ---------------------------------------------------------------

over_on<= '1' when pix_y (9 downto 6)=3 and

5 <= pix_x (9 downto 5) and pix_x(9 downto 5)<=13 else

'0';

row_addr_o<= std_logic_vector(pix_y(5 downto 2));

bit_addr_o<= std_logic_vector(pix_x(4 downto 2));

with pix_x(8 downto 5) select

char_addr_o <=

"1010011" when "0101",

"1010000" when "0110",

"1010010" when "0111",

"1010111" when others;

process(score_on,logo_on,rule_on,pix_x,pix_y,font_bit,char_addr_s,char_addr_l,char_addr_r,char_addr_o,

row_addr_s,row_addr_l,row_addr_r,row_addr_o,

bit_addr_s,bit_addr_l,bit_addr_r,bit_addr_o)

begin

  text_r<='0';

    text_g<='1';

    text_b<='1';

    if score_on ='1' then

char_addr <= char_addr_s;

row_addr<=row_addr_s;

bit_addr<= bit_addr_s;

if font_bit='1' then

   text_r<='0';

    text_g<='0';

    text_b<='1';

    end if;

    else if score_on ='1' then

char_addr <= char_addr_r;

row_addr<=row_addr_r;

bit_addr<= bit_addr_r;

if font_bit='1' then

  text_r<='0';

    text_g<='0';

    text_b<='1';

    end if;

else if logo_on ='1' then

char_addr <= char_addr_l;

row_addr<=row_addr_l;

bit_addr<= bit_addr_l;

if font_bit='1' then

text_r<='0';

    text_g<='0';

    text_b<='1';

    end if;

else 

char_addr <= char_addr_o;

row_addr<=row_addr_o;

bit_addr<= bit_addr_o;

if font_bit='1' then

  text_r<='0';

    text_g<='0';

    text_b<='1';

        end if;

    end if;

end process;

text_on <= score_on & logo_on & rule_on & over_on;

-- f o n t ROM i n t e r f a c e

rom_addr <= char_addr & row_addr;

font_bit <= font_word(to_integer(unsigned(not bit_addr)));

end Behavioral;

should include font_rom file?? i have it's .vhd file ??!! is it required in other formate??

i want to also add vga_sync.vhd file ....should it be .vhd file??

i use the referance of pong game text subsystem and want to edit vga syncronisation with it,,,,

Sorry Narenda, your code is pretty much incomprehensible in this form.

I assume that there was some indentation and that pasting it into E14 has lost that but you also should consider the following:

1) comments - if you want help with code think in terms of 1 comment for EVERY SINGLE LINE OF CODE

2) never declare two things at once, lines in the editor are free !

so not signal score_on,logo_on,rule_on,over_on: std_logic;

but

signal score_on : std_logic;               -- comment explaining what it's for

signal logo_on : std_logic;                 -- another comment

and so on.

3) Use white space it's free

so not text_b<='1';

but

text_b <= '1';                                   -- and every line needs a comment

4) Every process should have a name

Now to your question: I don't use Xilinx so I have never needed to use a block memory. I suggest that you make a little project who's sole purpose is to work out how to do this. All you need is a process to write to an address and then read from it (use a state machine). Then look up some examples: I Googled "spartan6 instantiate block ram" and found AR# 46748 - Spartan-6 FPGA Design Assistant - How to infer the use of block RAM and FIFO primitives in your HDL code which leads you to a .pdf and on page 130 you find:

--

-- Read-First Mode

--

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all;

entity rams_01 is

port (clk : in std_logic;

we : in std_logic;

en : in std_logic;

addr : in std_logic_vector(5 downto 0);

di : in std_logic_vector(15 downto 0);

do : out std_logic_vector(15 downto 0));

end rams_01;

architecture syn of rams_01 is

type ram_type is array (63 downto 0) of std_logic_vector (15 downto 0);

signal RAM: ram_type;

begin

process (clk)

begin

if clk’event and clk = ’1’ then

if en = ’1’ then

if we = ’1’ then

RAM(conv_integer(addr)) <= di;

end if;

do <= RAM(conv_integer(addr)) ;

end if;

end if;

end process;

end syn;

(Note the evil E14 cut and paste strikes again) There are lots of examples like this - read the whole chapter !!

Put this in a file of its own - give it the same name as the ram entity (in this case rams_01.vhd )

Then write a top level file that works as a test bench for this - (Xilinx tools may well make a test bench for you).

I can't tell how your project is constructed but it should be done with a top level file which calls up all the lower level entities and links them together - I use a graphical tool (Aldec HDL Block Diagram Editor)  to make these files but it doesn't come free with Xilinx tools. There may well be a graphical tool in the Xilinx toolset.

For future help you would do better to post a .zip file of the entire project  since it gets round trying to look at formatted files in E14 editor.

I know the style stuff seems tedious and nitpicking - but I assure you that now is the time to get into good habits. In 40 years+ of working on this kind of thingI have NEVER had an a problem with too many comments, but on countless occasionsI have had to waste time trying to work out what code is meant to be doing due to a lack of comments.

MK

Greeting dear !!!

have read tutorial on the ram interference...and now i am going to display font on the vga but in vga synchronization circuit same were wrong..the output does not supported by my lcd(1920*1200 also support 800*600 mode) lcd goes blank and go to power saving mode in short input not supported to lcd i dont know where i am wrong so please help me figur out where is misteck(or are mistechs:-)) firt of all for vga testing project i attached vga_sync_test.vhd  ,vga_sync.vhd and ucf file vga_synnaren togather but it doesn't work all files i have atteched with this post.........secondly in second project i want to display font actully four row of 128 character of 16*8 pixels on vga so i have atteched font_gen_top.vhd    ,font_test_gen.vhd,  vga_sync.vhd,   font_rom.vhd and ucf file named font_top_gen in the project sinthsize report there is successfully 4096*8 bit rom inferred but in this also same problem that it is enable to display ..may be folt in vga _sync....my fpga board use 50mhz clk and i want to use 800*600 mode with 72hz refresh rate......i am excited to display font so please help me...:-) i think  it can noy be atteched so i just copy here...

----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------

vga_sync_test:

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using

-- arithmetic functions with Signed or Unsigned values

use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating

-- any Xilinx primitives in this code.

library UNISIM;

use UNISIM.VComponents.all;

entity vga_test is

    Port ( clk : in  STD_LOGIC;

           reset : in  STD_LOGIC;

           sw : in  STD_LOGIC_VECTOR (2 downto 0);---switches

           rgb: inout std_logic_vector(2 downto 0);

           hsync : out  STD_LOGIC;

           vsync : out  STD_LOGIC);

end vga_test;

architecture Behavioral of vga_test is

signal rgb_reg:std_logic_vector(2 downto 0);

signal video_on:std_logic;

begin

--instantiate vga sync. circuit

vga_sync_unit:entity work.vga_sync

port map(clk=> clk,reset=> reset,hsync=> hsync,vsync=> vsync,video_on=> video_on,pixel_x=> open,pixel_y=> open);

--rgb buffer

process(clk,rgb_reg)

begin

if reset='1' then

rgb_reg<=(others=>'0');

elsif(clk'event and clk='1')

then rgb_reg<=sw;

end if;

end process;

process(video_on,rgb_reg)

begin

if video_on='1' then

rgb<=rgb_reg;

else

rgb<="000";

end if;

end process;

end Behavioral;

-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------

vga_sync.vhd:

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using

-- arithmetic functions with Signed or Unsigned values

use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating

-- any Xilinx primitives in this code.

library UNISIM;

use UNISIM.VComponents.all;

entity vga_sync is

    Port ( clk : in  STD_LOGIC;

           reset : in  STD_LOGIC;

           hsync : out  STD_LOGIC;

           vsync : out  STD_LOGIC;

           video_on : inout  STD_LOGIC;

           pixel_x : inout  STD_LOGIC_VECTOR (9 downto 0);

           pixel_y : inout  STD_LOGIC_VECTOR (9 downto 0)

               );

end vga_sync;

architecture Behavioral of vga_sync is

constant HD :integer := 800;-- horizontal display area

constant HF :integer := 64;-- horizontal fron porch

constant HB :integer := 56;-- horizontal back porch

constant HR :integer := 120;-- horizontal retrace

constant VD :integer := 600;-- vertical display area

constant VF :integer := 23;-- vertical front porch

constant VB :integer := 37;-- vertical back porch

constant VR :integer := 6;-- vertical retrace

--sync signals counter

signal v_count_reg ,v_count_next:unsigned(9 downto 0);

signal h_count_reg, h_count_next:unsigned(9 downto 0);

--output buffer

signal v_sync_reg,h_sync_reg:std_logic;

signal v_sync_next,h_sync_next:std_logic;

-- status signal

signal h_end,v_end,pixel_tick:std_logic;

begin

--regigtors..

process(clk,reset)

begin

if reset='1' then

v_count_reg<=(others=>'0');

h_count_reg<=(others=>'0');

v_sync_reg<='0';

h_sync_reg<='0';

elsif (clk'event and clk='1') then

v_count_reg<=v_count_next;

h_count_reg<=h_count_next;

v_sync_reg<=v_sync_next;

h_sync_reg<=h_sync_next;

end if;

end process;

--status

h_end<=  --end of horizontal counter

'1' when h_count_reg =(HD+HF+HB+HR-1)

else

'0';

v_end<=----------end of vertical counter

'1' when h_count_reg=(VD+VF+VB+VR-1)

else

'0';

process(h_count_reg,h_count_next,h_end)

begin

if h_end ='1' then

h_count_next<=(others=>'0');

else

h_count_next<= h_count_reg + 1;

end if;

end process;

process(v_count_reg,v_count_next,h_end,v_end)

begin

if h_end='1' then

if(v_end='1') then

v_count_next<=(others=>'0');

else

v_count_next<=v_count_reg +1;

end if;

else

v_count_next<=v_count_reg;

end if;

end process;

--test

--horizontal and vertical buffer to avoid the glitch

h_sync_next<=

'1' when (h_count_reg>=(HD+HF)) and (h_count_reg<=(HD+HF+HR-1))

else

'0';

v_sync_next<=

'1' when (v_count_reg>=(VD+VF)) and (v_count_reg<=(VD+VF+VR-1))

else

'0';

--video on/off

video_on<=

'1' when (h_count_reg<HD) and (v_count_reg<VD)

else

'0';

--output signal

hsync<= h_sync_reg;

vsync<=v_sync_reg;

pixel_x<=std_logic_vector(h_count_reg);

pixel_y<=std_logic_vector(v_count_reg);

end Behavioral;

---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------

vga_synaren----ucf file

NET "clk" LOC = "P126";

NET "hsync" LOC = "P95";

NET "vsync" LOC = "P97";

NET "rgb<0>" LOC = "P100";

NET "rgb<1>" LOC = "P99";

NET "rgb<2>" LOC = "P98";

NET "reset" LOC = "P111";

NET "sw<0>" LOC ="P112";

NET "sw<1>" LOC ="P15";

NET "sw<2>" LOC ="P114";

-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------

font_test_top.vhd:

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using

-- arithmetic functions with Signed or Unsigned values

--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating

-- any Xilinx primitives in this code.

--library UNISIM;

--use UNISIM.VComponents.all;

entity font_test_top is

    Port ( clk : in  STD_LOGIC;

           reset : in  STD_LOGIC;

           hsync : out  STD_LOGIC;

           vsync : out  STD_LOGIC;

           rgb : out  STD_LOGIC_VECTOR (2 downto 0));

end font_test_top;

architecture Behavioral of font_test_top is

signal pixel_x: std_logic_vector(9 downto 0);

signal pixel_y: std_logic_vector(9 downto 0);

signal video_on:std_logic;

signal rgb_reg: std_logic_vector(2 downto 0);

signal rgb_next: std_logic_vector(2 downto 0);

begin

--------instantate vga sync ckt

vga_sync_unit:entity work.vga_sync

port map( clk=>clk,reset=>reset,hsync=>hsync,vsync=>vsync,video_on=>video_on,pixel_x=>

pixel_x,pixel_y=>pixel_y);

-----instantate fontrom--------------------

font_gen_unit:entity work.font_test_gen

port map(clk=>clk,video_on=>video_on,pixel_x=>pixel_x,pixel_y=>pixel_y,rgb_text=>rgb_next);

-------rgb_buffer-----------------

process(clk)

begin

if (clk'event and clk='1') then

    rgb_reg<=rgb_next;

end if;

end process;

rgb<=rgb_reg;

end Behavioral;

-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------

font_test_gen.vhd:

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using

-- arithmetic functions with Signed or Unsigned values

use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating

-- any Xilinx primitives in this code.

library UNISIM;

use UNISIM.VComponents.all;

entity vga_sync is

    Port ( clk : in  STD_LOGIC;

           reset : in  STD_LOGIC;

           hsync : out  STD_LOGIC;

           vsync : out  STD_LOGIC;

           video_on : inout  STD_LOGIC;

           pixel_x : inout  STD_LOGIC_VECTOR (9 downto 0);

           pixel_y : inout  STD_LOGIC_VECTOR (9 downto 0)

               );

end vga_sync;

architecture Behavioral of vga_sync is

constant HD :integer := 800;-- horizontal display area

constant HF :integer := 64;-- horizontal fron porch

constant HB :integer := 56;-- horizontal back porch

constant HR :integer := 120;-- horizontal retrace

constant VD :integer := 600;-- vertical display area

constant VF :integer := 23;-- vertical front porch

constant VB :integer := 37;-- vertical back porch

constant VR :integer := 6;-- vertical retrace

--sync signals counter

signal v_count_reg ,v_count_next:unsigned(9 downto 0);

signal h_count_reg, h_count_next:unsigned(9 downto 0);

--output buffer

signal v_sync_reg,h_sync_reg:std_logic;

signal v_sync_next,h_sync_next:std_logic;

-- status signal

signal h_end,v_end,pixel_tick:std_logic;

begin

--regigtors..

process(clk,reset)

begin

if reset='1' then

v_count_reg<=(others=>'0');

h_count_reg<=(others=>'0');

v_sync_reg<='0';

h_sync_reg<='0';

elsif (clk'event and clk='1') then

v_count_reg<=v_count_next;

h_count_reg<=h_count_next;

v_sync_reg<=v_sync_next;

h_sync_reg<=h_sync_next;

end if;

end process;

--status

h_end<=  --end of horizontal counter

'1' when h_count_reg =(HD+HF+HB+HR-1)

else

'0';

v_end<=----------end of vertical counter

'1' when h_count_reg=(VD+VF+VB+VR-1)

else

'0';

process(h_count_reg,h_count_next,h_end)

begin

if h_end ='1' then

h_count_next<=(others=>'0');

else

h_count_next<= h_count_reg + 1;

end if;

end process;

process(v_count_reg,v_count_next,h_end,v_end)

begin

if h_end='1' then

if(v_end='1') then

v_count_next<=(others=>'0');

else

v_count_next<=v_count_reg +1;

end if;

else

v_count_next<=v_count_reg;

end if;

end process;

--test

--horizontal and vertical buffer to avoid the glitch

h_sync_next<=

'1' when (h_count_reg>=(HD+HF)) and (h_count_reg<=(HD+HF+HR-1))

else

'0';

v_sync_next<=

'1' when (v_count_reg>=(VD+VF)) and (v_count_reg<=(VD+VF+VR-1))

else

'0';

--video on/off

video_on<=

'1' when (h_count_reg<HD) and (v_count_reg<VD)

else

'0';

--output signal

hsync<= h_sync_reg;

vsync<=v_sync_reg;

pixel_x<=std_logic_vector(h_count_reg);

pixel_y<=std_logic_vector(v_count_reg);

end Behavioral;

Greeting dear !!!

have read tutorial on the ram interference...and now i am going to display font on the vga but in vga synchronization circuit same were wrong..the output does not supported by my lcd(1920*1200 also support 800*600 mode) lcd goes blank and go to power saving mode in short input not supported to lcd i dont know where i am wrong so please help me figur out where is misteck(or are mistechs:-)) firt of all for vga testing project i attached vga_sync_test.vhd  ,vga_sync.vhd and ucf file vga_synnaren togather but it doesn't work all files i have atteched with this post.........secondly in second project i want to display font actully four row of 128 character of 16*8 pixels on vga so i have atteched font_gen_top.vhd    ,font_test_gen.vhd,  vga_sync.vhd,   font_rom.vhd and ucf file named font_top_gen in the project sinthsize report there is successfully 4096*8 bit rom inferred but in this also same problem that it is enable to display ..may be folt in vga _sync....my fpga board use 50mhz clk and i want to use 800*600 mode with 72hz refresh rate......i am excited to display font so please help me...:-) i think  it can noy be atteched so i just copy here...

----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------

vga_sync_test:

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using

-- arithmetic functions with Signed or Unsigned values

use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating

-- any Xilinx primitives in this code.

library UNISIM;

use UNISIM.VComponents.all;

entity vga_test is

    Port ( clk : in  STD_LOGIC;

           reset : in  STD_LOGIC;

           sw : in  STD_LOGIC_VECTOR (2 downto 0);---switches

           rgb: inout std_logic_vector(2 downto 0);

           hsync : out  STD_LOGIC;

           vsync : out  STD_LOGIC);

end vga_test;

architecture Behavioral of vga_test is

signal rgb_reg:std_logic_vector(2 downto 0);

signal video_on:std_logic;

begin

--instantiate vga sync. circuit

vga_sync_unit:entity work.vga_sync

port map(clk=> clk,reset=> reset,hsync=> hsync,vsync=> vsync,video_on=> video_on,pixel_x=> open,pixel_y=> open);

--rgb buffer

process(clk,rgb_reg)

begin

if reset='1' then

rgb_reg<=(others=>'0');

elsif(clk'event and clk='1')

then rgb_reg<=sw;

end if;

end process;

process(video_on,rgb_reg)

begin

if video_on='1' then

rgb<=rgb_reg;

else

rgb<="000";

end if;

end process;

end Behavioral;

-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------

vga_sync.vhd:

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using

-- arithmetic functions with Signed or Unsigned values

use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating

-- any Xilinx primitives in this code.

library UNISIM;

use UNISIM.VComponents.all;

entity vga_sync is

    Port ( clk : in  STD_LOGIC;

           reset : in  STD_LOGIC;

           hsync : out  STD_LOGIC;

           vsync : out  STD_LOGIC;

           video_on : inout  STD_LOGIC;

           pixel_x : inout  STD_LOGIC_VECTOR (9 downto 0);

           pixel_y : inout  STD_LOGIC_VECTOR (9 downto 0)

               );

end vga_sync;

architecture Behavioral of vga_sync is

constant HD :integer := 800;-- horizontal display area

constant HF :integer := 64;-- horizontal fron porch

constant HB :integer := 56;-- horizontal back porch

constant HR :integer := 120;-- horizontal retrace

constant VD :integer := 600;-- vertical display area

constant VF :integer := 23;-- vertical front porch

constant VB :integer := 37;-- vertical back porch

constant VR :integer := 6;-- vertical retrace

--sync signals counter

signal v_count_reg ,v_count_next:unsigned(9 downto 0);

signal h_count_reg, h_count_next:unsigned(9 downto 0);

--output buffer

signal v_sync_reg,h_sync_reg:std_logic;

signal v_sync_next,h_sync_next:std_logic;

-- status signal

signal h_end,v_end,pixel_tick:std_logic;

begin

--regigtors..

process(clk,reset)

begin

if reset='1' then

v_count_reg<=(others=>'0');

h_count_reg<=(others=>'0');

v_sync_reg<='0';

h_sync_reg<='0';

elsif (clk'event and clk='1') then

v_count_reg<=v_count_next;

h_count_reg<=h_count_next;

v_sync_reg<=v_sync_next;

h_sync_reg<=h_sync_next;

end if;

end process;

--status

h_end<=  --end of horizontal counter

'1' when h_count_reg =(HD+HF+HB+HR-1)

else

'0';

v_end<=----------end of vertical counter

'1' when h_count_reg=(VD+VF+VB+VR-1)

else

'0';

process(h_count_reg,h_count_next,h_end)

begin

if h_end ='1' then

h_count_next<=(others=>'0');

else

h_count_next<= h_count_reg + 1;

end if;

end process;

process(v_count_reg,v_count_next,h_end,v_end)

begin

if h_end='1' then

if(v_end='1') then

v_count_next<=(others=>'0');

else

v_count_next<=v_count_reg +1;

end if;

else

v_count_next<=v_count_reg;

end if;

end process;

--test

--horizontal and vertical buffer to avoid the glitch

h_sync_next<=

'1' when (h_count_reg>=(HD+HF)) and (h_count_reg<=(HD+HF+HR-1))

else

'0';

v_sync_next<=

'1' when (v_count_reg>=(VD+VF)) and (v_count_reg<=(VD+VF+VR-1))

else

'0';

--video on/off

video_on<=

'1' when (h_count_reg<HD) and (v_count_reg<VD)

else

'0';

--output signal

hsync<= h_sync_reg;

vsync<=v_sync_reg;

pixel_x<=std_logic_vector(h_count_reg);

pixel_y<=std_logic_vector(v_count_reg);

end Behavioral;

---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------

vga_synaren----ucf file

NET "clk" LOC = "P126";

NET "hsync" LOC = "P95";

NET "vsync" LOC = "P97";

NET "rgb<0>" LOC = "P100";

NET "rgb<1>" LOC = "P99";

NET "rgb<2>" LOC = "P98";

NET "reset" LOC = "P111";

NET "sw<0>" LOC ="P112";

NET "sw<1>" LOC ="P15";

NET "sw<2>" LOC ="P114";

-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------

font_test_top.vhd:

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using

-- arithmetic functions with Signed or Unsigned values

--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating

-- any Xilinx primitives in this code.

--library UNISIM;

--use UNISIM.VComponents.all;

entity font_test_top is

    Port ( clk : in  STD_LOGIC;

           reset : in  STD_LOGIC;

           hsync : out  STD_LOGIC;

           vsync : out  STD_LOGIC;

           rgb : out  STD_LOGIC_VECTOR (2 downto 0));

end font_test_top;

architecture Behavioral of font_test_top is

signal pixel_x: std_logic_vector(9 downto 0);

signal pixel_y: std_logic_vector(9 downto 0);

signal video_on:std_logic;

signal rgb_reg: std_logic_vector(2 downto 0);

signal rgb_next: std_logic_vector(2 downto 0);

begin

--------instantate vga sync ckt

vga_sync_unit:entity work.vga_sync

port map( clk=>clk,reset=>reset,hsync=>hsync,vsync=>vsync,video_on=>video_on,pixel_x=>

pixel_x,pixel_y=>pixel_y);

-----instantate fontrom--------------------

font_gen_unit:entity work.font_test_gen

port map(clk=>clk,video_on=>video_on,pixel_x=>pixel_x,pixel_y=>pixel_y,rgb_text=>rgb_next);

-------rgb_buffer-----------------

process(clk)

begin

if (clk'event and clk='1') then

    rgb_reg<=rgb_next;

end if;

end process;

rgb<=rgb_reg;

end Behavioral;

-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------

font_test_gen.vhd:

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using

-- arithmetic functions with Signed or Unsigned values

use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating

-- any Xilinx primitives in this code.

library UNISIM;

use UNISIM.VComponents.all;

entity vga_sync is

    Port ( clk : in  STD_LOGIC;

           reset : in  STD_LOGIC;

           hsync : out  STD_LOGIC;

           vsync : out  STD_LOGIC;

           video_on : inout  STD_LOGIC;

           pixel_x : inout  STD_LOGIC_VECTOR (9 downto 0);

           pixel_y : inout  STD_LOGIC_VECTOR (9 downto 0)

               );

end vga_sync;

architecture Behavioral of vga_sync is

constant HD :integer := 800;-- horizontal display area

constant HF :integer := 64;-- horizontal fron porch

constant HB :integer := 56;-- horizontal back porch

constant HR :integer := 120;-- horizontal retrace

constant VD :integer := 600;-- vertical display area

constant VF :integer := 23;-- vertical front porch

constant VB :integer := 37;-- vertical back porch

constant VR :integer := 6;-- vertical retrace

--sync signals counter

signal v_count_reg ,v_count_next:unsigned(9 downto 0);

signal h_count_reg, h_count_next:unsigned(9 downto 0);

--output buffer

signal v_sync_reg,h_sync_reg:std_logic;

signal v_sync_next,h_sync_next:std_logic;

-- status signal

signal h_end,v_end,pixel_tick:std_logic;

begin

--regigtors..

process(clk,reset)

begin

if reset='1' then

v_count_reg<=(others=>'0');

h_count_reg<=(others=>'0');

v_sync_reg<='0';

h_sync_reg<='0';

elsif (clk'event and clk='1') then

v_count_reg<=v_count_next;

h_count_reg<=h_count_next;

v_sync_reg<=v_sync_next;

h_sync_reg<=h_sync_next;

end if;

end process;

--status

h_end<=  --end of horizontal counter

'1' when h_count_reg =(HD+HF+HB+HR-1)

else

'0';

v_end<=----------end of vertical counter

'1' when h_count_reg=(VD+VF+VB+VR-1)

else

'0';

process(h_count_reg,h_count_next,h_end)

begin

if h_end ='1' then

h_count_next<=(others=>'0');

else

h_count_next<= h_count_reg + 1;

end if;

end process;

process(v_count_reg,v_count_next,h_end,v_end)

begin

if h_end='1' then

if(v_end='1') then

v_count_next<=(others=>'0');

else

v_count_next<=v_count_reg +1;

end if;

else

v_count_next<=v_count_reg;

end if;

end process;

--test

--horizontal and vertical buffer to avoid the glitch

h_sync_next<=

'1' when (h_count_reg>=(HD+HF)) and (h_count_reg<=(HD+HF+HR-1))

else

'0';

v_sync_next<=

'1' when (v_count_reg>=(VD+VF)) and (v_count_reg<=(VD+VF+VR-1))

else

'0';

--video on/off

video_on<=

'1' when (h_count_reg<HD) and (v_count_reg<VD)

else

'0';

--output signal

hsync<= h_sync_reg;

vsync<=v_sync_reg;

pixel_x<=std_logic_vector(h_count_reg);

pixel_y<=std_logic_vector(v_count_reg);

end Behavioral;

font_test_gen.vhd

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using

-- arithmetic functions with Signed or Unsigned values

use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating

-- any Xilinx primitives in this code.

library UNISIM;

use UNISIM.VComponents.all;

entity font_test_gen is

    Port ( clk : in  STD_LOGIC;

           video_on : inout  STD_LOGIC;

           pixel_x  : inout  STD_LOGIC_VECTOR (9 downto 0);

           pixel_y  : inout  STD_LOGIC_VECTOR (9 downto 0);

           rgb_text : out    std_logic_vector ( 2 downto 0)

              );

end font_test_gen;

architecture Behavioral of font_test_gen is

signal rom_addr:std_logic_vector(10 downto 0);

signal char_addr:std_logic_vector(6 downto 0);

signal row_addr:std_logic_vector(3 downto 0);

signal bit_addr:std_logic_vector(2 downto 0);

signal font_word:std_logic_vector(7 downto 0);

signal font_bit,text_bit_on:std_logic;

begin

-----instantiatiate font ROM

font_unit:entity work.font_rom

port map( clka=>clk,addra=>rom_addr,douta=>font_word);

-----fontRAM interface

char_addr<=pixel_y(5 downto 4 ) & pixel_x(7 downto 3);

row_addr<=pixel_y(3 downto 0);

rom_addr<= char_addr & row_addr;

bit_addr<=pixel_x(2 downto 0);

font_bit<= font_word(to_integer(unsigned(not bit_addr)));

--"on" region limited to top left corner

text_bit_on<=

                font_bit when pixel_x(9 downto 8)="00" and

                                    pixel_y(9 downto 6)="0000" else

                                    '0';

----------rgb multiplexing circuit

process(video_on,font_bit,text_bit_on)

begin

if video_on='0' then

        rgb_text<="000";--blank

else

  if text_bit_on='1' then

        rgb_text<="010";----green

  else

        rgb_text<="000";----black

  end if;

end if;

end process; 

end Behavioral;

font_test_gen.vhd

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using

-- arithmetic functions with Signed or Unsigned values

use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating

-- any Xilinx primitives in this code.

library UNISIM;

use UNISIM.VComponents.all;

entity font_test_gen is

    Port ( clk : in  STD_LOGIC;

           video_on : inout  STD_LOGIC;

           pixel_x  : inout  STD_LOGIC_VECTOR (9 downto 0);

           pixel_y  : inout  STD_LOGIC_VECTOR (9 downto 0);

           rgb_text : out    std_logic_vector ( 2 downto 0)

              );

end font_test_gen;

architecture Behavioral of font_test_gen is

signal rom_addr:std_logic_vector(10 downto 0);

signal char_addr:std_logic_vector(6 downto 0);

signal row_addr:std_logic_vector(3 downto 0);

signal bit_addr:std_logic_vector(2 downto 0);

signal font_word:std_logic_vector(7 downto 0);

signal font_bit,text_bit_on:std_logic;

begin

-----instantiatiate font ROM

font_unit:entity work.font_rom

port map( clka=>clk,addra=>rom_addr,douta=>font_word);

-----fontRAM interface

char_addr<=pixel_y(5 downto 4 ) & pixel_x(7 downto 3);

row_addr<=pixel_y(3 downto 0);

rom_addr<= char_addr & row_addr;

bit_addr<=pixel_x(2 downto 0);

font_bit<= font_word(to_integer(unsigned(not bit_addr)));

--"on" region limited to top left corner

text_bit_on<=

                font_bit when pixel_x(9 downto 8)="00" and

                                    pixel_y(9 downto 6)="0000" else

                                    '0';

----------rgb multiplexing circuit

process(video_on,font_bit,text_bit_on)

begin

if video_on='0' then

        rgb_text<="000";--blank

else

  if text_bit_on='1' then

        rgb_text<="010";----green

  else

        rgb_text<="000";----black

  end if;

end if;

end process; 

end Behavioral;