Some FPGA Beginner Questions

Question

Hi element14!

Some time ago I've watched a talk of the nand2tetris course/project. If you've never heard of it you can check it out here: http://www.nand2tetris.org/ Basically it is a course designed to build a computer from the very ground up. It starts with logic gates and goes all the way up to programming a small game project (hence the name nand2tetris). There is also a video available from someone who has been doing the course on FPGA hardware ( http://www.youtube.com/watch?v=UHty1KKjaZw ).

[At one point in the above linked youtube video you can see the designation "ep2c8q208", which should mean the project is running on Altera Cyclone II hardware.]

I've always been curious about doing something with FPGA hardware, but never had any idea of a feasible, yet interesting-result-yielding project. Well, as you can probably guess, up until now that is

During my university days I attended an FPGA workshop and I've read some stuff about the hardware components and the available course material, so I think I kind of have an idea about the difficulty of the project. But since everything I've been reading just made me more excited, I decided I absolutely want to give this a shot. Now there's a lot of FPGA information out there, so I'm surely still missing a lot of important information, but I would like to get started and think the best way to learn is to actually experiment with a real FPGA instead of wasting too much time with HDL simulations only to become used to functions that aren't going to synthesize on the board anyway.

So I now would like to ask you about some things I'm still unsure about and would like to have clarified before buying an expensive development kit. I've read several articles about Altera and Xilinx and right now my choice would be a Spartan 3E Starter Board - this one to be exact: http://shop.embedded-projects.net/index.php?module=artikel&action=artikel&id=549

The main questions I'm having right now:

- Is there a general reason that would argue against getting the Spartan E3 board?

- I actually have no idea how powerful an FPGA really is.. but assuming it's running on Cyclone II hardware, it probably should run on a Spartan 3 as well? Or is that in itself already a stupid question, as FPGA comparison doesn't work so easily?

- As you can see, the price for the above board is about 150 Euro, which translates to something just short of $200. Yet I continue to find offers (on ebay or other websites) where boards are being sold for under $150 but even include small screens(!)* What am I missing here? Did I pick an especially expensive outlet, or is there something shady about these cheap deals..?

- In general, who is more newbie-friendly, Altera or Xilinx? (I've worked with VHDL before, which I think is Xilinx, right? Altera's Quartus is probably very similar?)

- From how I understand the FPGA toolchain, in the above linked offer there should be everything included to get me going.. right? o_O

I also have this second candidate: http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,400,836&Prod=ATLYS

- Maybe I'm an idiot, but as I read the offer, *only* the board is sold? I.e., in contrast to the first offer, I would need additional stuff to get something running on the board?

- It also strikes me as a mayor drawback that there is not really an output option besides a few LEDs.. which for me would be very annoying; I'm already unhappy about the board linked before *only* having a small display (which in itself, however, is awesome to have of course).

- This might also be a stupid question: I remember from back in the FPGA workshop I mentioned that getting a number-display to run is not that hard at all. How much more effort is it to get something displayed on a screen (either an attached one or a PC screen accessed via one of the available ports)?

And as a final question: I've also seen some very much smaller boards than the ones linked here, that are also much cheaper.. are the boards I'm looking it overkill for what I'd like to do with them? Or does actually the contrary hold, and such a project wouldn't even run on one of the smaller boards available?

Thanks for your help!

Cheers,

pan

________________________

* Here for example:

http://www.sainsmart.com/evaluation-board/fpga-cpld-board/new-ep2c8q208c8n-development-board-kit-fpga-altera-cyclone-nios-ii-with-2-4-lcd.html

johnbeetem · Answer

Hi Christian, I just saw your discussion today. I don't check the element14 FPGA page much since activity is rare. There's some good FPGA discussion in this thread at the Raspberry Pi group, including some other development boards. I've done a lot of design with the Xilinx Spartan-3A. It's a nice architecture. For learning FPGAs, there's really no need to jump to the Spartan-6 unless you need the increased capacity for a specific project. Although the Spartan-6 ICs cost about the same as Spartan-3A, the boards are still quite a bit more expensive. Lattice had eval boards for their small-FPGA iCE40 series with promotional pricing of US$19 for a short time, but I think they're back to the standard US$39, so for that price you're better off spending a little more for a 200K gate Spartan-3A, e.g., the US$55 XESS XuLA-200 . I haven't tried that board myself, but the specs are attractive. All the major FPGAs can synthesize from VHDL or Verilog. JMO/YMMV: If you like to type and love the Ada language, go with VHDL. If you like C and prefer more concise notations, go with Verilog. My preference of the two is Verilog, but neither is really a good fit for FPGA design. According to my recollection, VHDL was conceived for specifying and simulating behavior of VLSI designs. Verilog was conceived for generating test vectors and expected behavior. Neither was conceived as a language for synthesizing logic, so you have to be inventive to get the synthesizer to produce the logic you really want. The best language I've used for that was Altera's AHDL, but I don't think it's an option any more. FPGAs are very powerful and a lot of fun. You get to design digital chips with zero cost for making logic errors. Have lots of fun and please report problems and progress.

michaelkellett · Answer

I'm going to offer some advice which has worked well for me over the last 10 years. Forget Xilinx and Altera and download the Lattice toolset - not as capable as the full Xilinx kit but good enough to take you along way and much simpler. I use the paid for version every day (along with other tools) and it works very well for me. Xilinx make some wonderful big FPGAs but Lattice have a better offering (IMO) at the low end. There is nothing as simple as WinCupl for FPGA. There are cheap Lattice dev kits for the Ice, Mach and XP2 ranges - pick the part you might want to play with and download the right tools - (ask if not obvious which) - then get the tools working and only bother to buy the kit if you're happy. MK

michaelkellett · Answer

You can use VHDL perfectly well with the Xilinx, Altera, Lattice or Micro-Semi free tools. John uses Verilog and I use VHDL so you can ask one of us if you get stuck whichever language you use. John's suggested approach to learning is good advice. It's easy to find lots of simple examples on the web but the important thing is to actually implement them on your hardware. Don't forget to use the simulator before you try the code on an actual chip - you can learn a great deal by simulating ! MK

michaelkellett · Answer

Sorry Narenda, your code is pretty much incomprehensible in this form. I assume that there was some indentation and that pasting it into E14 has lost that but you also should consider the following: 1) comments - if you want help with code think in terms of 1 comment for EVERY SINGLE LINE OF CODE 2) never declare two things at once, lines in the editor are free ! so not signal score_on,logo_on,rule_on,over_on: std_logic; but signal score_on : std_logic; -- comment explaining what it's for signal logo_on : std_logic; -- another comment and so on. 3) Use white space it's free so not text_b<='1'; but text_b <= '1'; -- and every line needs a comment 4) Every process should have a name Now to your question: I don't use Xilinx so I have never needed to use a block memory. I suggest that you make a little project who's sole purpose is to work out how to do this. All you need is a process to write to an address and then read from it (use a state machine). Then look up some examples: I Googled "spartan6 instantiate block ram" and found AR# 46748 - Spartan-6 FPGA Design Assistant - How to infer the use of block RAM and FIFO primitives in your HDL code which leads you to a .pdf and on page 130 you find: -- -- Read-First Mode -- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity rams_01 is port (clk : in std_logic; we : in std_logic; en : in std_logic; addr : in std_logic_vector(5 downto 0); di : in std_logic_vector(15 downto 0); do : out std_logic_vector(15 downto 0)); end rams_01; architecture syn of rams_01 is type ram_type is array (63 downto 0) of std_logic_vector (15 downto 0); signal RAM: ram_type; begin process (clk) begin if clk’event and clk = ’1’ then if en = ’1’ then if we = ’1’ then RAM(conv_integer(addr)) <= di; end if; do <= RAM(conv_integer(addr)) ; end if; end if; end process; end syn; (Note the evil E14 cut and paste strikes again) There are lots of examples like this - read the whole chapter !! Put this in a file of its own - give it the same name as the ram entity (in this case rams_01.vhd ) Then write a top level file that works as a test bench for this - (Xilinx tools may well make a test bench for you). I can't tell how your project is constructed but it should be done with a top level file which calls up all the lower level entities and links them together - I use a graphical tool (Aldec HDL Block Diagram Editor) to make these files but it doesn't come free with Xilinx tools. There may well be a graphical tool in the Xilinx toolset. For future help you would do better to post a .zip file of the entire project since it gets round trying to look at formatted files in E14 editor. I know the style stuff seems tedious and nitpicking - but I assure you that now is the time to get into good habits. In 40 years+ of working on this kind of thingI have NEVER had an a problem with too many comments, but on countless occasionsI have had to waste time trying to work out what code is meant to be doing due to a lack of comments. MK

michaelkellett · Answer

A simple counter example for LED twinkles ! There must be a way to add a text file - someone please tell how ! MK

michaelkellett · Answer

@Christian, There is a univeral law (and it really is universal) sometimes referred to as the first law of Thermodynamics but better expressed as " There is no such thing as a free lunch". Xilinx are quite upfront about it - if you pay a bit for the software you can disable WebTalk - if you use the "free" version on of their paybacks is they get to collect data. If you don't like X and A then look at the smaller players' offerings - I use Lattice parts because I find the company much easier to deal with than X or A. You could also try MicroSemi (used to be Actel). Lattice have some simple FPGAs on very cheap and simple boards. Still no free lunches but a selection of different ways to pay ! Michael Kellett

Former Member · Answer

Thank you very much Micheal and John l!! I am starting to learn basic exampls with this website . http://www.fpgacenter.com/examples/index.php.......but displaying text and image on vga is my project so it has time deadline it's my first project so please if you have any help regarding that also please tell me..thanks naren.

michaelkellett · Answer

@ Curtiss, As you say the Papilio is a reasonable price but there are two things I think should make beginners think carefully about it: It comes with some very complex FPGA stuff ready to go - this won't help you get really into FPGAs very easily and it's not clear (to me) what simple tutorial stuff there is. It's based on a rather old (by Xilinx standards) chip - nothing wrong with Spartan 3 but there are much better parts now for the same or less money. Michael Kellett

Former Member · Answer

Michael, Quick reply.... Thanks. Lattice was not a name I was familiar with. Yes, before buying a board, I was looking at the toolsets first. I don't mind paying for a good tool to support the devices. But more than a few hundred is out of the question, primarily because I don't want to spend the money and find out that I prefer a different manufacturer. My next question, which I suspect the answer is no, but I'll ask anyway... Do any of these tools cross devices? Can a single VHDL compiler create code for Xlinix, Altera, and others? Obviously, if one did exist, it wouldn't be a freebie because it's not supported by the manufacturer. More digging... More waiting... :-) And I was so eager to buy a board to start playing with! -Scott

michaelkellett · Answer

Well actually there ARE universal tools but they are not cheap: I use Aldec HDL which is a multi language vendor agnostic simulator (costs about £12k) - so I generate VHDL which in theory is FPGA vendor independent but in practice you always need to use specific vendor libraries to access things like RAM or multipliers so your code quickly gets locked in unless you are very careful and put a lot of work into independence. You get a cut down free version with the Lattice tools. I think Xilinx use their own simulator and Altera use ModelSim. You can buy (I think) a universal synthesizer but it will be very expensive - no point at your level of work. The free version of Synplify that comes with the Lattice tools is fine (but works only for Lattice), Xilinx have their own synthesizer (works only for Xilinx). The only limitation with the free Lattice toolset (at first) is that it doesn't support FPGAs with high speed SERDES which means you can't do PCIE (and a few other fancy things) but by the time you need to do that the cost of the paid up Diamond license is small change in the whole project. If I were you I'd look at the Lattice Brevia kit - (Farnell 2253073, £32.68) - it's a bit old hat (using a fairly old FPGA) but it's cheap and has plenty of potential. Once you've got your toes in the water you could go for the ECP3 VERSA kit which is £177 from Farnell but gets you dual Gbit Ethernet and DDRAM (and a whole lot of complexity which will be overwhelming at first ). MK

michaelkellett · Answer

I only had a very quick look at this site but I strongly recommend that you find another - why - because its examples use deprecated and non standard libraries which will cause you trouble in the end. (They use IEEE.STD_LOGIC_ARITH .AL L; which is not really a standard at all, despite the name, you should use numeric_std - see here for why http://vhdlguru.blogspot.co.uk/2010/03/why-library-numericstd-is-preferred.html Have a look here: https://www.doulos.com/knowhow/vhdl_designers_guide/ much better. Lattice, Xilinx and Altera have lots of examples. MK

michaelkellett · Answer

I can't see where you posted a link to the book but I think you mean "FPGA Prototyping by VHDL Examples" by Pong P Chu which is widely pirated on the web and available as a .pdf. As a guide this book is sadly lacking since it has only a very brief discussion of simulation. Simulation is the KEY to getting any design (other than the most trivial) to work on an FPGA in a reasonable time. I can't possibly go though your VHDL and find bugs in it - there is far too much and it would take far too long. So the solution is for you to simulate it - I'm sure the Xilinx tools include a usable simulator and test bench generator. Run a simulation that generates and displays graphically the VGA outputs - actually it is usually better to test the design in small pieces before you put it all together but since you think it's complete you may as well test the whole thing. If the VGA outputs are correct (and if you don't know what correct VGA looks like you can't test the design) then run the design on a chip and check that you have the same results in hardware as in simulation. If the simulation shows bad VGA data then work back in the simulation until you find the problem. If the hardware isn't doing what the simulation does then add hardware check points and use a scope (Xilinx may offer a virtual scope thing but I haven't ever used it so I can't comment on how good it is - I don't find the Lattice equivalent to be much use.) In most FPGA designs producing the verification/testing code and running it to completion takes longer than writing the original code. Time spent carefully planning and designing the job will reduce the coding and verification/testing time. Once you start simulating please feel free to come back and ask about things that don't do what you want. (BTW - one quick check worth doing is to compare the actual use of FPGA resources with what you expect - it is very common with a new design to find that where you expected to use 10k logic blocks, 24 block rams and 78 DSP (example numbers only !!) blocks the synthesizer/fitter reports only a small fraction of these as being used - this will be because somewhere you don't actually use an output or miss out a clock and the synthesizer optimizes away most of your design (for the very good reason that it can't read your mind and most of the design isn't actually doing anything). MK

johnbeetem · Answer

narendra rathod wrote: 
 
 yes john i had also started with simple colorbox,colorbar and color pattern project but in those example the vga _sync is slightly different than above ,they all are worked well but now i am going with p.changs book... 
 OK, if you have examples that work and another that doesn't there's a couple of things you can do: 1. Compare a working example to the non-working example to see what's different. It might be something as simple as having different master clock frequencies. Analyzing other people's source code is a good way to improve your understanding of VHDL and you can see what VHDL style works best for you. 2. Start with a working example (so you can generate a good VGA display) and add your own VHDL code to display characters. Start with something simple like displaying the same character over and over (using a constant look-up table) indexed by VGA row and column. Once that's working use a Block RAM containing a single character. Then fill the Block RAM with the full character set and index it by VGA row and column to display the whole character set. IMO it's useful to learn from examples, and useful to parts of source code from examples with permission, but trying to get examples to work together "as is" can be a lot of work and frustration. JMO/YMMV

michaelkellett · Answer

Go Altera if you like but I don't think John or I can help you much then with specifics - I don't like third party dev boards for FPGA (or anything else) - this may be prejudice but I've always had problems with them. Mouser sell Lattice stuff and have the Brevia kit in stock: LFXP2-5E-B2-EVN Lattice | Mouser This is a link to the UK Mouser web site but the stock will be in the US. Even cheaper is the ICE40HX1K-STICK-EVN Lattice | Mouser but I think this is a bit light weight for you - it only has the 1k LUT ICE40 part and limited pin access. MK

michaelkellett · Answer

Chip Scope is Xilinx's virtual scope tool, used in hardware test/verification not during simulation: http://www.xilinx.com/itp/xilinx10/isehelp/ise_c_process_analyze_design_using_chipscope.htm Plan Ahead is an advanced design tool which you don't need to bother with yet. You need to read the Xilinx documents relevant to the simulator you mean to use - you can write (often automatically) a test bench to exercise your top level entity. This is probably where you should start. Later on you should try to get intot the habbit of making test benches for your lower level entities as you write them. MK

michaelkellett · Answer

Hello Scott, It has some nice things on board: LatticeXP2 FPGA: LFXP2-5E-6TN144C 2 Mbit SPI Flash Memory 1 Mbit SRAM On-board USB controller for JTAG programming (FTDI - FT2232H) 2x20 and 2x5 Expansion Headers Push-buttons for general purpose I/O and reset 4-bit DIP switch for user-defined inputs Eight status LEDs for user-defined outputs see this page: XP2 Brevia2 Dev Kit - Lattice Semiconductor MK

michaelkellett · Answer

Go to this page: Licensing - Lattice Semiconductor and request the free license. (Paid for licenses take a day or two to arrive, a free one may be more automatic. You may need to register some personal details (this is inevitable because although Lattice are keen to sell chips they use third party software components from companies who need to keep track of where it's used because that's all they make.) Then go here http://www.latticesemi.com/en/Products/DesignSoftwareAndIP/FPGAandLDS/LatticeDiamond.aspx#_229A1F76B8DF4E0098F41B8CC7935… and download and install Diamond. It installs a complete development environment which includes the download tools. MK

michaelkellett · Answer

When the synthesis and fitter tools have finished they produce lots of reports which you should have a look at. You'll find that if you didn't use a clock in your design then there won't be a pin assigned to one, so to answer your question, An FPGA design which consists entirely of combinatorial logic will not need a clock. In reality such designs are very rare indeed, all FPGA's from A,L M and X are intended to implement synchronous designs so clocks (often several different ones) are needed. For example, if you had an 8 digit 7 seg display to drive you could do it with 8 hex -> 7 seg decoders but it would almost certainly be more efficient to use 1 and share it, which would require some clocking. As soon as you get on to anything serious you need state machines and they will need clocks. (This is because of the way FPGAs work - I think (but can't quote a proof) that any time dependent logic design can be implemented synchronously or asynchronously from a logical point of view - it's just that FPGAs don't do asynchronous stuff well.) I haven't forgotten the example - it may happen today. MK

johnbeetem · Answer

Michael Kellett wrote: 
 
 (This is because of the way FPGAs work - I think (but can't quote a proof) that any time dependent logic design can be implemented synchronously or asynchronously from a logical point of view - it's just that FPGAs don't do asynchronous stuff well.) 
 Asynchronous design is a nightmare. It's all hazards and races. It's important for all digital engineers to have studied asynchronous design, because it's the theory that backs up why it's so critical to meet setup, hold, and minimum clock pulse width requirements. Asynchronous theory normally requires that logic operates in "fundamental mode". In fundamental mode, only one input changes at a time, and the effects of that change must settle before the next input change. If two inputs change at the same time (e.g., the clock and data inputs of a flip-flop) or one changes before the effects of the other have settled, you can have unpredictable behavior including metastability. Asynchronous theory is tractable if you stick with fundamental mode. If you can't assume fundamental mode, it becomes very difficult in general. Synchronous design is a special case of asynchronous design. In synchronous design, data signals propagate through combinational logic (with no loops) and they can change simultaneously as long as the effects settle before the next clock edge. When the clock edge occurs, you normally assume that all registers driven by that clock update simultaneously, i.e., the changed outputs of those registers do not propagate so fast that they change inputs to registers that haven't finished updating. As long as you use global clock nets, this requirement is satisfied by the FPGA circuits and you don't need to worry about it. I've kept things simple by assuming edge-triggered registers with a single clock. Using latches and multiple clocks gets a lot more interesting

Some FPGA Beginner Questions

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