FPGA: trigger on both flanks of a clock to toggle output

Question

I tried to take a naïve approach to (if needed) toggle an output pin either on the rising or falling edge of clock signal.

Line 17 below:

entity variable_clock is
    Port ( 
      clk_i    : in  STD_LOGIC;
      resetn_i : in  STD_LOGIC;
      ticks_i  : in  STD_LOGIC_VECTOR (7 downto 0);
      clk_o    : out STD_LOGIC
    );
end variable_clock;

architecture Behavioral of variable_clock is
  signal counter_s: natural range 0 to 2**ticks_i'length-1 := 0;
  signal clk_out_s: STD_LOGIC := '0';
begin

process (clk_i, resetn_i)
begin
  if rising_edge(clk_i) then
    if resetn_i = '0' then
      counter_s <= 0;
      clk_out_s <= '0';
    else
      if counter_s >= unsigned(ticks_i) then -- >= because the value can change
        counter_s <= 0;
        clk_out_s <= not clk_out_s;
      else
        counter_s <= counter_s + 1;
      end if;
      clk_o <= clk_out_s;
    end if;
  end if;
end process;

end Behavioral;

This synthesises without errors, but the output is identical when I use

  if rising_edge(clk_i) then

or

  if (rising_edge(clk_i) or falling_edge(clk_i)) then

Not double speed when using both edges, as the naïve me would expect.

Internet has many opinions and warnings on this subject - both for simulation and synthesis. Your thoughts?

michaelkellett · Answer

I've never tried this so all suggestions are theory only ! Don't expect it to be easy to fool the tools into allowing this - FPGAs do not expect double data rate stuff internally. VHDL and simulation won't help you much - VHDL can do it easily - it's the synthesiser that chokes. Simple way - use a pll and double the clock speed But you are using a big fat and powerful Xilinx chip - its has DDR hardware on it's outputs. So you should be able to clock 2 bits in and get single double rate bits out. This will require a really good poke into the FPGA output hardware. There will be Xilinx examples you can look at. In fact - you may be able to go much further. For high speed serial ports for SERDES many FPGAs have "gearboxes" - which will take an 8 bit input at clock Q and output a bit stream at 8 x Q. (Often support other ratios too) MK

wolfgangfriedrich · Answer

I always try to remind myself that the if rising_edge () statement is a special case as it does get synthesized into the clock input of a flip-flop instead of some logic gates/lookup tables. Putting more conditions into that if clause, especially the falling_edge() function would make the synthesizer throw up in some form or another as there is no easy hardware equivalent to implement that. I would hope that there would be at least some warnings from the tool, that some statements get ignored. - W.

FPGA: trigger on both flanks of a clock to toggle output

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