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Forum Vivado and Zynq: TRI-STATE help
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  • zynq
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Related

Vivado and Zynq: TRI-STATE help

Jan Cumps
Jan Cumps over 3 years ago

I'm trying to write i2c code for Zynq, in VHDL.
I have difficulties creating a TRI-STATE pin.

The output logic should be: the pin is either pulled down to 0, or open-collector.
I have a pull-up resistor between that pin and VCC (3.3 V).
I'm expecting that if I write '0', it is low. When I write 'Z', it's open collector and pulled high by my pullup.
But in my design, the pin stays low. 0.62 V.

I thought, from reading up, that I should be done by:

  • defining the pin as INOUT
  • when you want to drive it low, assign '0'.
  • when you want to drive it open collector, assign 'Z'.
  • put an external pullup between pin and VCC

I created a testbed that puts the pin in "Z' mode, except when reset is asserted (via an external button).
In my testbed I also added a test pin, that I attach to an LED, that is high when the reset is asserted.
I connected a multimeter to the output.

The LED behaves as expected. It lights up when I assert the reset.
But the tri-state pin stays low, whether I write '0' or 'Z' to it. 

entity tristate_test is
    Port ( 
    reset_n: in std_logic;
    reset_out: out std_logic;
    tristate_pin : inout std_logic);
end tristate_test;

architecture Behavioral of tristate_test is

begin

reset_active: process (reset_n) is

begin
  if (reset_n = '0') then
    tristate_pin <= '0';
    reset_out <= '1';
  else
    tristate_pin <= 'Z';
    reset_out <= '0';
  end if;
end process reset_active;

end Behavioral;

Here is how I set the constraint:

image

set_property PACKAGE_PIN Y18 [get_ports tristate_pin_0]
set_property IOSTANDARD LVCMOS33 [get_ports tristate_pin_0]
set_property DRIVE 12 [get_ports tristate_pin_0]

Schema:

image

PMOD A pin 1 is PACKAGE_PIN Y18

What am I doing wrong?

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Top Replies

  • jc2048
    jc2048 over 3 years ago +4
    It might be a problem with hierarchy with the drag-and-drop stuff. An answer to this support question suggests that you need to set the synthesis to flatten the hierachy so that the tristate-ness can propagate…
  • jc2048
    jc2048 over 3 years ago in reply to bhfletcher +4
    Once you understand that the block-based design is an entity that could be used as part of a larger, more traditional design, the issue with the top-level wrapper becomes clearer. If the user is just using…
  • rachaelp
    rachaelp over 3 years ago +3
    Hi Jan, Just create the tristate in an assignment and not in a process. Not sure why what you have isn't working, have you looked at the schematic for what it's creating in Vivado? I guess maybe it's…
  • jc2048
    0 jc2048 over 3 years ago in reply to bhfletcher

    Once you understand that the block-based design is an entity that could be used as part of a larger, more traditional design, the issue with the top-level wrapper becomes clearer. If the user is just using the blocks, then it's desirable for the design software to maintain the wrapper on any changes to the block design. If it's part of a wider design, you probably don't want the block stuff to keep regenerating the wrapper on changes and overwriting stuff that has been added and it's then up to the user to maintain the wrapper [their top-level entity].

    I think that some of the difficulty here might be because it's valid to describe, in VHDL, a tristate internal bus between entities. Doesn't matter whether it can be done any particular hardware or not, the synthesis just has to get on with it and, if necessary, translate it into an equivalent logic form (usually it would constitute a multiplexer in some arrangement). At the top level things are unambiguous - the 'tristateness' must be referring to an IO pin. But a tristate at the top of the blocks, one level (or more) down, might just be forming a bus with other entities in the design and not go anywhere near an IO pin. Alternatively, as another example, there could be an internal tristate bus that simply feeds an output pin. So something extra that clears up the ambiguity is necessary.

    If anyone is interested, there's an historical twist to this because Xilinx FPGAs, once upon a time, did actually include internal tristate busses and they could be designed with quite explicitly.

    Here's how 'long lines' are shown in the 1989 Xilinx databook. Notice the tristate drivers.

    image

    Here's part of an application note showing how the 'long line' could be used for fast multiplexing of the various addresses to implement a DRAM controller.

    image

    I did a design around that time which controlled VRAM and can just about remember using tristate buffers and an internal bus in that way for multiplexing the RAS, CAS, etc (it was done with schematic capture and the part library had a '125' part, ie equivalent functionally to a 74125 tristate buffer, that you could use). Can't remember if I was using 2000 or 3000 series parts.

    I imagine it was a bit of a liability for them at the time because of the way you might disrupt the device operation if you got the control of the buffers wrong.

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