I started my FPGA journey with VHDL. Hence, I'm quite comfortable with VHDL. I tried learning Verilog, but it seems redundant to me as I already knew one HDL, so I gave up on learning Verilog.
However, while pursuing my master's, I saw that Verilog had become the most popular HDL and was being taught in my university and demanded in the industry.
I also find that many of the participants in the Spartan_Migration challenge are using Verilog.
Which HDL do you prefer and why? Have you tried learning VDHL or Verilog while you already knew one of them?
I like VHDL because it appears more structured and it was the first HDL I learned during my engineering days.
