Snickerdoodle board on FLOSS Weekly

I haven't watched the video since most of my computers don't have sound hooked up, so this comment may already be addressed in the video:

Snickerdoodle has a very impressive price for a Zynq board, but what's it doing on FLOSS weekly?  Don't you have to use the proprietary Xilinx Vivado software to program the Zynq FPGA?

The closed toolchain is not ideal, but this is pretty much an universal problem for FPGA design.

I think FLOSS (Free/Libre/Open Source Software) is still relevant if a FPGA based project like this is releasing HDL "source code".

I've not gotten clarification on yet on whether their board is Open Source Hardware.  I hope that they will release schematics, PCB layout and BOM.  Could you comment, rcousins?

fustini We're going to be posting the schematics & BOM in the next week or two (just have a few final tweaks to make to the power supply subsystem that will further decrease the standby/sleep power consumption).

johnbeetem gdstew Of course, you could always synthesize an FPGA *in* the FPGA and run whichever open-source toolchain you'd like. While it's disappointing the tools aren't open, FPGAs are fundamentally the most open source silicon component you could ever ask for - you are in complete control over what the chip is doing at the gate level.

We can only make open the software that's in our control (with the two primary closed-source items being the FPGA toolchain and the TI radio firmware). There are numerous technical (and, of course, "business") reasons these companies haven't totally opened up these tools, but we don't really believe/have faith in the 'sit and wait' method when it comes to changing paradigms or corporate philosophies.

We just want to provide powerful tools for people to create and learn about new things. It's still possible to be a highly productive carpenter regardless of open/closed the designs of your hammer/saw/drill are. Ultimately, if enough people get this technology into their hands and truly want to affect change, we believe the "people" will find a way.

As an aside, if someone has an open FPGA toolchain that has been proven to work with Zynq, we're more than happy to try it out and see how we can support it.

-Ryan

Drew: I hope that they will release schematics, PCB layout and BOM.

Schematics and BOM definitely, never really understood the need for PCB layout unless there is a layout related problem. If there is, there is not much I can do to fix it

especially in today's 6 or more layer SBC world. Cloning ? I like seeing all the different products with different capabilities. This has not really hurt pricing competition

either as a lot of the competing SBCs' prices hover reasonably around the Raspberry Pi price and I recently bought a 1.6 GHz quad-core 1 GB Orange Pi PC for a little

less than 19 USD including shipping.

Ryan

After over 40 years I've learned to live the fact that certain things in the electronics industry are just going to be proprietary. As long as I can get good tools at reasonable prices,

which has always been the biggest problem I've had with proprietary tool sets, I can live with it. The Vivado Design Suite is free which is a very good price ! I haven't had time

to check out the licensing restrictions yet (won't really need it until March 2016) but i assume this is for non-commercial designs which is what I want to do for now anyway. I

would like to see open tool sets that would remove such restrictions available, I just don't think it is going to happen for certain products which include FPGAs and GPUs.

P.S. 99% FUNDED !!!!!!  20:41 CDT. I think we're going to make it

Ryan Cousins wrote:

 

John Beetem gdstew Of course, you could always synthesize an FPGA *in* the FPGA and run whichever open-source toolchain you'd like. While it's disappointing the tools aren't open, FPGAs are fundamentally the most open source silicon component you could ever ask for - you are in complete control over what the chip is doing at the gate level.

I understand that FPGA vendors are afraid to release their bitstream formats for reasons that seem good to them, and so their tools are therefore proprietary.  My objection is that some projects claim that they are FLOSS (Free-as-in-Liberty Open-Source Software) when a key component cannot be programmed with FLOSS tools.  BeagleBoard and BeagleBone are up front that the GPU is proprietary and cannot be programmed with FLOSS tools, but the GPU is a small part of BeagleBoard/Bone and many projects don't need it and can therefore be fully FLOSS.  Except for the GPU, there is enough information in the TI SoC tomes to write bare-metal applications.

RasPi is more of a stretch.  As I understand it, the Broadcom documentation doesn't really give you enough information to write your own operating system and you must reverse-engineer from the Linux source code and use a "binary blob" to boot the GPU.  OTOH, they do document the GPU but I haven't heard whether RasPi users have been successful writing their own GPU applications and integrating them into actual RasPis.

Yes, FPGAs are indeed powerful components but I don't agree with calling them an "open-source silicon component".  Yes, you can use them as a component of an OSHW design, but since you can't program them using a FLOSS toolchain (except for Lattice iCE40 thanks to the amazing IceStorm) you don't have any of RMS's "four freedoms".  If the proprietary tools don't give you the correct result, you can't go into the source code and figure out why.  You have to try a bunch of "black magic" and play with different ways of expressing a design at the source code level to cajole the software into doing the right thing.  This sort of nonsense is exactly what led RMS to his crusade.

"Synthesizing an FPGA in an FPGA" can be useful, but as far as I can tell it makes terribly inefficient use of silicon resources and you cannot get good performance.  I think my Flavia project Flavia: the Free Logic Array is a wonderful tool for teaching about programmable logic, since it's small and fast: you can recompile and download a small design in a second or two.  IMO that's awesome compared to the longueurs you face using proprietary tools -- assuming you have the patience to download them in the first place and get the license to work.  OTOH, Flavia is really only suitable for small projects.  You can do a much bigger project with a tiny Lattice iCE40-HX1K and IceStorm than you can do with Flavia and the much larger Xilinx Spartan-6 LX9.

Now, maybe there's a much better way to do an "FPGA within an FPGA".  However, I would think that if it were possible and practical we would have seen it by now.

I should also mention that Flavia and other projects that manipulate Xilinx bitstreams can only do so because of the availability of Xilinx Design Language (XDL): Taming the Wild Bitstream.  I think I read somewhere that XDL is no longer available with Vivado.  I don't know if there's a substitute for it.

johnbeetem By that logic, no ARM or x86 project or platform could *ever* be considered "FLOSS." Is anyone expecting ARM or Intel to provide the masks for their chips? How do you change the arrangement of the gates on the STM32 sitting on my desk? I'm a bit confused as to why FPGAs are somehow held to a different standard of "openness" than any other (closed) silicon component simply because they give you more granular control over the function and configuration of the chip. Oh, and the tools are free.

Ignoring that for a moment, Zynq has a hard ARM core and you can use any open source tool you'd like to do whatever you want with the microprocessor - the I/O are simply routed through the programmable fabric (using the same AXI busses as any other ARM uC/uP).

michaelkellett Hopefully a $55 board with an ARM processor, FPGA, and wireless falls into the category of 'low cost' - we've even taken care of the "talking to Xilinx" part for you

Thanks, gdstew! Fully funded this morning...

The Zynq is not in the running re low cost FPGAs  (and isn't meant to be) - the Lattice parts are MUCH simpler, come in packages you can hand solder (at least some of them) and in volume can cost less than $1 - not aimed at the same market at all.

But the cost of using a Zynq or any other SOC FPGA isn't just money - in order to get it to do anything much (ie to make serious use of the processor) you need a full blown OS which implies many megabytes of code - which will be sourced from a third party somehow (free or whatever).

If the application needs all this that's fine but if you just want an FPGA you'll do better not to have to maintain all the other stuff. In a lot of my work we end up with an FPGA (small by X standards at between 8 and 35k LUTs) and a Cortex M4 micro - if the Zynq chip was free we still wouldn't use it because the total cost of building and maintaining the product would go up.

Finally, how can I put this nicely, when a snag occurs with a chip you need to talk directly to the people who made it - the last thing you need is someone else doing your talking.

Your board may well be very nice (it's certainly a cheap way of getting  a Zynq chip)  and I wish you well with it but the cost of actually doing anything is only dominated by the cost of a dev board in home/hobby projects.

MK

Ryan Cousins wrote:

 

John Beetem By that logic, no ARM or x86 project or platform could *ever* be considered "FLOSS." Is anyone expecting ARM or Intel to provide the masks for their chips? How do you change the arrangement of the gates on the STM32 sitting on my desk? I'm a bit confused as to why FPGAs are somehow held to a different standard of "openness" than any other (closed) silicon component simply because they give you more granular control over the function and configuration of the chip. Oh, and the tools are free.

ARM and x86 silicon is not software.  It's hardware.  It's proprietary hardware and nobody expects ARM or x86 to become OSHW.

However, ARM and x86 silicon are a hardware platform that can be used for FLOSS (Free-as-in-Liberty Open-Source Software).  The ARM and x86 intruction sets are published, including both assembly language and their binary codings.  So as a programmer, you can write FLOSS that runs on those platforms and when you distribute source code your users have the option of modifying your source code for their own needs and recompiling it for their hardware.

In addition, you can write a compiler for any language you want and generate ARM or x86 machine language.  You are not dependent on the chip maker.  You are not required to use (for example) PL/M for the x86 machine or (as a silly example) APL for the ARM.  You buy the chip, the manufacturer tells you what the instruction bits do, and you can write whatever software you want.  You have freedom.

You don't get that kind of freedom with FPGAs other than iCE40.  You can't write your own compiler because you don't know what the machine-language bits do.  You have to use the Free-as-in-Beer tools from the FPGA vendor.  If they don't do what you want there's nothing you can do about it.  Yes, that's adequate for the majority of FPGA users and you can produce useful chips -- I do this professionally as a free-lance FPGA designer.  But there are a bunch of things that are impractical.  My favorite example is reconfigurable computing: FPGA tool bottleneck stalls HPC.  Reconfigurable computing doesn't sell a lot of chips for an FPGA vendor, so there's no motivation for them to produce tools that support it.  If FPGAs supported FLOSS, that wouldn't be a problem: other people could create that software.  The fact that the bitstream formats are proprietary means that they can't, and an amazingly useful FPGA application is stalled.

I'm not asking Xilinx or any other FPGA vendor to provide masks, just like I don't expect Intel or ARM to document how they implement their instruction sets.  I just want to know how to set the bits in FPGA bitstreams to perform the functions documented in their architecture documentation.  That's all I need for FLOSS.

Hope this helps

<< but the GPU is a small part of BeagleBoard/Bone and many projects don't need it and can therefore be fully FLOSS.

>> And others do need it which makes it not FLOSS. Is this some kind of quantum FLOSS ? You make this argument

all the time and it still does not make sense. By the very definition there is no FLOSS when your SoC contains proprietary

hardware no matter how fine you try (and try, and try) to split that hair.

<< As I understand it, the Broadcom documentation doesn't really give you enough information to write your own operating system and you must reverse-engineer from the Linux source code and use a "binary blob" to boot the GPU.

>> BSD ? RISCOS ? There has also bee a port to an RTOS. I don't remember which RTOS but I was part of a

discussion about porting it in these forums and the person trying to do it made the same argument as you. After

pointing him to the Broadcom documentation he was able to complete the port. Your "understanding" needs updating.

>> Since the GPU documentation has been released, an assembler and disassembler have been made available

which allows anyone to disassemble the boot code. Since BSD, RISCOS, a couple of bare metal projects and

the RTOS port I spoke of earlier use the existing boot loader, I'm not sure why using the binary blob is such a

bad thing but it is nice to be able to produce an alternative.

<< OTOH, they do document the GPU but I haven't heard whether RasPi users have been successful writing their own GPU applications and integrating them into actual RasPis.

>> I have seen a couple of projects that do. Google it with "using raspberry pi GPU" and learn.

<< If the proprietary tools don't give you the correct result, you can't go into the source code and figure out why.

>> I probably couldn't figure it out even if I had the source code. High speed logic routing and optimization

of large FPGA designs is beyond my skill set and I would venture a guess that it is beyond yours and most

other peoples' in the business as well.

<< "Synthesizing an FPGA in an FPGA" can be useful, but as far as I can tell it makes terribly inefficient

use of silicon resources and you cannot get good performance. 

>> I'm not real big on this idea either for exactly the same reason.

<< I think my Flavia project Flavia: the Free Logic Array is a wonderful tool for teaching about programmable logic, since it's small and fast: you can recompile and download a small design in a second or two.  IMO that's awesome compared to the longueurs you face using proprietary tools -- assuming you have the patience to download them in the first place and get the license to work.  OTO FH,lavia is really only suitable for small projects.  You can do a much bigger project with a tiny Lattice iCE40-HX1K and IceStorm than you can do with Flavia and the much larger Xilinx Spartan-6 LX9.

>> As you say, the Vivado Design Suite is not a tool for teaching about programmable logic. It is a fully

professional tool for creating large, high speed logic designs. Comparing these two objectives and the

complexity of the tools needed are like comparing building and an Estes model rocket to a Saturn V. It

just doesn't work as a reasonable argument.

>> It took about 20 minutes to download the 6.9 GB VDS and another few minutes to download some other files.

Modern high speed Internet (mine is "only" 50 Mb/s although I have seen it hit, but not hold closer to 80 on

one or two occasions) is a wonderful thing. YMMV.

<< but the GPU is a small part of BeagleBoard/Bone and many projects don't need it and can therefore be fully FLOSS.

>> And others do need it which makes it not FLOSS. Is this some kind of quantum FLOSS ? You make this argument

all the time and it still does not make sense. By the very definition there is no FLOSS when your SoC contains proprietary

hardware no matter how fine you try (and try, and try) to split that hair.

<< As I understand it, the Broadcom documentation doesn't really give you enough information to write your own operating system and you must reverse-engineer from the Linux source code and use a "binary blob" to boot the GPU.

>> BSD ? RISCOS ? There has also bee a port to an RTOS. I don't remember which RTOS but I was part of a

discussion about porting it in these forums and the person trying to do it made the same argument as you. After

pointing him to the Broadcom documentation he was able to complete the port. Your "understanding" needs updating.

>> Since the GPU documentation has been released, an assembler and disassembler have been made available

which allows anyone to disassemble the boot code. Since BSD, RISCOS, a couple of bare metal projects and

the RTOS port I spoke of earlier use the existing boot loader, I'm not sure why using the binary blob is such a

bad thing but it is nice to be able to produce an alternative.

<< OTOH, they do document the GPU but I haven't heard whether RasPi users have been successful writing their own GPU applications and integrating them into actual RasPis.

>> I have seen a couple of projects that do. Google it with "using raspberry pi GPU" and learn.

<< If the proprietary tools don't give you the correct result, you can't go into the source code and figure out why.

>> I probably couldn't figure it out even if I had the source code. High speed logic routing and optimization

of large FPGA designs is beyond my skill set and I would venture a guess that it is beyond yours and most

other peoples' in the business as well.

<< "Synthesizing an FPGA in an FPGA" can be useful, but as far as I can tell it makes terribly inefficient

use of silicon resources and you cannot get good performance. 

>> I'm not real big on this idea either for exactly the same reason.

<< I think my Flavia project Flavia: the Free Logic Array is a wonderful tool for teaching about programmable logic, since it's small and fast: you can recompile and download a small design in a second or two.  IMO that's awesome compared to the longueurs you face using proprietary tools -- assuming you have the patience to download them in the first place and get the license to work.  OTO FH,lavia is really only suitable for small projects.  You can do a much bigger project with a tiny Lattice iCE40-HX1K and IceStorm than you can do with Flavia and the much larger Xilinx Spartan-6 LX9.

>> As you say, the Vivado Design Suite is not a tool for teaching about programmable logic. It is a fully

professional tool for creating large, high speed logic designs. Comparing these two objectives and the

complexity of the tools needed are like comparing building and an Estes model rocket to a Saturn V. It

just doesn't work as a reasonable argument.

>> It took about 20 minutes to download the 6.9 GB VDS and another few minutes to download some other files.

Modern high speed Internet (mine is "only" 50 Mb/s although I have seen it hit, but not hold closer to 80 on

one or two occasions) is a wonderful thing. YMMV.

Gary Stewart wrote:

 

After pointing him to the Broadcom documentation he was able to complete the port. Your "understanding" needs updating... Google it with "using raspberry pi GPU" and learn.

 

....

 

I probably couldn't figure it out even if I had the source code. High speed logic routing and optimization of large FPGA designs is beyond my skill set and I would venture a guess that it is beyond yours and most other peoples' in the business as well.

I'm delighted to hear that people are successful using the RasPi GPU in practice.  I may check it out myself some time.  I've looked at the GPU instruction set and it's a nice SIMD architecture.  Amazing amount of performance there in a $20 - $35 board.

Regarding your experience with design automation software: I would venture to say that very few people have the motivation to learn Linux kernel programming, yet there are enough that do to produce an amazingly great FLOSS operating system.  In fact, I've done a great deal of design automation research and teaching in my career and the optimization algorithms involved are not any more complex that those used by optimizing compilers.  The lesson of Linux is that the number of people required to get a project like this started is one and that a small number of people joining in can do great things (confirmed by the lessons of Unix, C, and ARM).  Indeed, a small, indpendent project not hampered by millions of lines of legacy code can do amazing things.

In case it isn't clear, I'm not in the least bit interested in looking at Xilinx source code.  I just want them to document their bitstream format -- something already done by every major CPU maker -- so that the open-source community can write our own tools.

<< Regarding your experience with design automation software: I would venture to say that very few people have the motivation to learn Linux kernel programming, yet there are enough that do to produce an amazingly great FLOSS operating system.

>> If you have a different experience with free PCB software I would love to hear where I can pick up a free version that really matches any of the commercial products.

Clearly the "Linux experience" doesn't apply here.

<< In fact, I've done a great deal of design automation research and teaching in my career and the optimization algorithms involved are not any more complex that those used by optimizing compilers.

>> Yet after 15+ years they don't appear in free PCB software. Perhaps you could be the one, or are you not that interested (see what I mean ?). Also I would venture

another guess that there are significant differences between PCB and FPGA optimization due to such things as vastly tighter physical contraints, route restictions due to

physical gate/cell/LUT layout and interconnection number limits, greater noise and crosstalk problems, power, clock distribution, and the difference in the scale of the

number of routes/connections. And that's just for one device/family.

<< The lesson of Linux is that the number of people required to get a project like this started is one and that a small number of people joining in can do great things (confirmed by the lessons of Unix, C, and ARM).  Indeed, a small, indpendent project not hampered by millions of lines of legacy code can do amazing things.

>> Yet again even after 15+ years all that wonderfulness has not happened when it comes to relatively "simple" PCB design software. Why would the much more

complicated FPGA tool set(s) be different ? One mans being hampered by legacy code is another mans years of experience and hard learned lessons. In the case

of FPGAs I'll go with experience and years of bugs fixed instead of years of fixing bugs. Also, ARM does not really belong in that group at all, it is now and has

always been a fully proprietary product.

<< In case it isn't clear, I'm not in the least bit interested in looking at Xilinx source code.

<<"If the proprietary tools don't give you the correct result, you can't go into the source code and figure out why."

>> So there are exceptions ?

<< I just want them to document their bitstream format

>> Yes, and I have said on several occasions that I would like to see that too, but it is not going to happen no matter how many times you or I say we want it. So now what ?

The next best thing is reasonably priced fully professional tools that take full advantage of the intimate knowledge of the physical devices and years of experience with building

tools for them. Until recently these tools have been non-existent and they are still the exception.

>> something already done by every major CPU maker

<< You can't distribute the "software" to make your own ARM core or any other major CPU core for that matter in a gate array or FPGA without getting sued.

Gary Stewart wrote:

 

If you have a different experience with free PCB software I would love to hear where I can pick up a free version that really matches any of the commercial products.  Clearly the "Linux experience" doesn't apply here.

I don't design PC boards these days so I haven't checked out the latest open-source or freeware PCB software packages.  I've heard that some are quite good.  It's not really necessary to match a commercial product -- you just need something that's adequate for your needs.  I've watched layout gurus work with commercial software packages and frankly I'm not impressed with the usability of the software I've seen.

Anyway, here are some open-source or freeware PCB links:

KiCAD: http://www.eetimes.com/author.asp?doc_id=1320005

Low Cost PCB tools: http://www.eetimes.com/author.asp?section_id=36&doc_id=1319924

Software is too expensive: http://www.element14.com/community/thread/31852

Gary Stewart wrote:

 

Yet after 15+ years they don't appear in free PCB software. Perhaps you could be the one, or are you not that interested (see what I mean ?).  Also I would venture another guess that there are significant differences between PCB and FPGA optimization due to such things as vastly tighter physical contraints, route restictions due to

physical gate/cell/LUT layout and interconnection number limits, greater noise and crosstalk problems, power, clock distribution, and the difference in the scale of the number of routes/connections. And that's just for one device/family.

Placement and routing for FPGAs is simpler than PCB because you don't have to deal with so many design rules.  Routing is quite easy once you know where the PIPs are.  I don't need to be "the one" -- arachne-pnr is in my experience a fine tool for Lattice iCE40.

Gary Stewart wrote:

 

Yes, and I have said on several occasions that I would like to see [FPGA vendors document their tool chains] too, but it is not going to happen no matter how many times you or I say we want it. So now what?

If you and/or I are the only ones who ask for it, of course nothing is going to happen.  But if everyone who cares about the issue advocates for it, the spark can catch on and become a fire.

Meanwhile, there have been and are projects to reverse-engineer bitstream formats.  There have been several attempts for Xilinx FPGAs, but I don't know of any that completed the job.  IceStorm chose a simpler FPGA and is the only one I know of that has a complete mapping.  This is a fantastic achievement and Lattice appears to realize that this is a good thing for Lattice: it increases interest in their chips and differentiates their chips from Brands X and A.  When Brand X and A realize that Lattice is taking away business, they'll be motivated to document their bitstreams.  I've been waiting 25 years for this.  A few more is nothing.

You have to be careful about reverse-engineering in the USA.  Europe allows reverse-engineering for interoperability, which is probably why all the bitstream reverse-engineering work I've seen is from Europe.

Last point... I have seen cpu architecture simulated in software not efficient but great debugging tool.

Clem