2-Minute FPGAs: Synchronous vs Asynchronous Flip Flops

Synchronous vs Asynchronous Flip Flops

FPGA Group | The Summer of FPGAs - Agenda

Join Whitney Knitter of Knitronics for two minutes as we discuss the logic and computer science behind programming with Lattice's ICE40 tinyFPGA! Today we discuss synchronous vs asynchronous flip flops! This is the third part in a series of videos and blog posts over the course of the Summer of FPGA.

Supplemental Content

Summer of FPGAs: 2-Minute FPGAs with Whitney Knitter

Getting Started with the TinyFPGA & Lattice Diamond 3.12 on Ubuntu 18.04

Additional Parts:

Product Name
iCE40 FPGAiCE40 FPGA
tinyFPGAtinyFPGA

Summer of FPGA 2-Minute FPGAs - More Videos Coming Soon!

Top Comments

albertabeef over 3 years ago

Very important topic
The use of synchronous resets is often part of design methodology guides.

As an example, in UG949 (UltraFast Design Methodology Guide), Xilinx indicates:
If a reset is needed, Xilinx recommends code synchronous resets. Synchronous resets have many advantages over asynchronous resets.
Thank you for the great topic Whitney

Here's an idea for another topic : Flip-Flops versus Latches

Regards,
Mario.
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knitronics over 3 years ago in reply to javagoza

Thank you!
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javagoza over 3 years ago

Very well explained. Thanks Whitney for going a bit further with this explanation.
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