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Documents Programmable Electronic Load - Analyse the Summing Node Zero Point
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  • Author Author: Jan Cumps
  • Date Created: 1 Dec 2017 4:08 PM Date Created
  • Last Updated Last Updated: 15 May 2020 3:38 PM
  • Views 10270 views
  • Likes 8 likes
  • Comments 107 comments
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Programmable Electronic Load - Analyse the Summing Node Zero Point

This blog documents investigates the feedback node of the electronic load that Robert Peter Oakes, jc2048 and Jan Cumps are designing.

It's an important spot in the load's design. It measures the set point and the feedback from the output.

When the output is driven to 0, it should be on a potential as close as possible to 0 V.

On the first prototype it's -0.2 V. Not so much off, but the negative value  influences our ADC measurements.

This document checks how we can get this node to 0 V.

image

 

Because this document is evolving, some comments below may be out of sync with the content. That's because the content is adapted based on the conversation.

The measurements taken here are based on the original design, without R32 in place and U3B + tied to ground.

The current sense side of R7 is connected to ground, and a variable negative voltage from 0 V down is applied to the current sense side of R8 to simulate current being sensed.

 

The circuit isn't complex. The set point is driven by a DAC. It's set to 0 for this test.

The second input to this node is OpAmp 3C. It has both inputs tied to ground so should theoretically have 0 V at the output.

On my board I measure a potential of -0.212V at the left side of R33.

I hope to get this closer to 0 V to ease the ADC a bit - its performance degrades with negative voltage at its inputs.

Like the other blogs for the electronic load, this is a working document that will be updated with findings from anyone who wants to chime in.

 

Behaviour at 0V

 

buzy image

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Top Comments

  • jc2048
    jc2048 over 8 years ago in reply to Robert Peter Oakes +4
    As you say, changing the op-amp is one possibility. There are bipolar op-amps with much lower bias currents, but an alternative nowadays is a precision CMOS op-amp (you'd have to check whether other characteristics…
  • Robert Peter Oakes
    Robert Peter Oakes over 8 years ago +3
    To hopefully simplify things a little We have this, Upper op amp is simply to provide an inversion of the measured value back tot he ADC, hence the gain of -1 Lower right op amp measures the volts across…
  • jc2048
    jc2048 over 8 years ago in reply to Jan Cumps +3
    Love the advertisement for "John's excellent probes". It's like one those things from the old days of American TV where the presenter would suddenly turn, look very earnestly at the camera, and start reading…
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  • Jan Cumps
    Jan Cumps over 8 years ago

    I get excited about small things image but the image below is the result of controlling our electronic load and a power supply in a LabVIEW script.

    image

    Two times the PSU is set to a certain voltage to mimic load current, then one of the load's ADCs sampled to validate that.

    First time the output is set to 0 V and the load should report 0 amps. The second time to 0.02V and the load should report 0.4 A.

    There are several reasons why the returned values aren't spot on, but that's not the purpose of the automation. The automation is there to reveal the errors and give a repeatable test case.

     

    This is how it looks like in the LabVIEW run-time.

    image

    I still have to learn how I can make the 'set PSU then sample" block reusable and how to make good loops. Still it's satisfying to know that all tools are up to the game and that it's just skills that are lacking.

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  • Jan Cumps
    Jan Cumps over 8 years ago in reply to Jan Cumps

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  • Jan Cumps
    Jan Cumps over 8 years ago in reply to Jan Cumps

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