Digilent, a National Instruments Company

Digilent, an NI company, has been at the forefront of innovation since 2000, crafting hardware and software solutions that empower engineers, researchers, educators, and scientists to design and test with unparalleled flexibility. Our customizable solutions cater to both seasoned professionals and emerging engineers, accelerating development while maintaining a low barrier to entry.

We're committed to accessibility, offering competitive pricing, portable products, and comprehensive documentation. With a global presence spanning three continents, Digilent ensures speedy and cost-effective access to our products through an extensive distribution network. Specializing in Xilinx-based FPGA development boards, USB-based test and measurement devices, a variety of expansion modules for customizing applications, and the respected MCC DAQ product line, our design philosophy champions your creativity. By emphasizing speed, modularity, customizability, world class support, and open-source principles, we provide the building blocks while you bring the brilliance.

Pmod Pin	Arduino Uno Pins
Vcc	3V3
GND	GND
SCK	13 (SCK)
MOSI	11 (MOSI)
CS	10
D/C	9
RES	8
VCCEN	3V3
PmodEN	3V3

Drive DC Motor with Digilent Pmod H-bridge with Feedback Inputs and Arduino Uno

alexwonglik1

This projects showcase how to use Digilent Pmod HB5Pmod HB5 H-bridge driver and Arduino Uno to drive the DC motor. The Pmod HB5 offers a 2A H-bridge circuit to drive small- to medium-sized DC motors. Two sensor feedback pins are incorporated into the motor connection header and are specifically designed to work with the Digilent motor/gearbox, which incorporates quadrature encoder feedback. An Arduino Uno can be used to control the motor direction and speed. Digilent Pmod BTN pushbutton let users input the speed and direction.

First of all, you need to connect the Pmod HB5 and Pmod BTN to Arduino Uno. To drive the DC motor, you need to connect a 9V battery to Pmod HB5.

Wiring instructions:

Pmod HB5 <----------> Arduino Uno <----------> Pmod BTN

VCC to 5V to VCC

GND to GND to GND

DIR to 2 to -

EN to 3 to -

- to 4 to BTN0

- to 5 to BTN1

- to 6 to BTN2

Then, you can enter the below Arduino code in the Arduino IDE and upload the sketch.

/************************************************************************


  Test of the Pmods HB5 and BTN


*************************************************************************
  Project description:  
  The pushbutton BTN0 changes the direction of the motor
  The pushbutton BTN1 increases the motor speed.
  The pushbutton BTN2 decreases the speed of the motor.
  The motor speed is displayed on the serial monitor.
***********************************************************************/


//defining connections
#define DIR   2   
#define EN    3
#define BTN_0 4
#define BTN_1 5
#define BTN_2 6 


void setup() {
  Serial.begin(9600); // Initialization of the serial monitor
  pinMode(DIR, OUTPUT); // Configure DIR to an output pin
  digitalWrite(DIR, LOW); // Set DIR Low 
  pinMode(EN, OUTPUT); // Configure EN to an output pin
  digitalWrite(EN, LOW); // Set EN Low
  pinMode(BTN_0, INPUT); // Configure BTN_0 to input pin
  pinMode(BTN_1, INPUT); // Configure BTN_1 to input pin
  pinMode(BTN_2, INPUT); // Configure BTN_2 to input pin
}


unsigned int spd = 0; //define motor speed as unsigned integer and set initial motor speed to 0
bool dir = LOW;       //define dir (motor direction) as a Boolean variable and set initial direction to low 


void loop() {
  //read buttons
  bool b0 = digitalRead(BTN_0); // Reading BTN_0
  bool b1 = digitalRead(BTN_1); // Reading BTN_1
  bool b2 = digitalRead(BTN_2); // Reading BTN_2


  //increment motor speed by 5 if button 1 is pressed and spd is less than the maximum duty cycle (255)
  if (spd < 255 && b1) {
    spd += 5;
  }


  //decrement motor speed if button 2 is pressed and spd is greater than 0 
  if (spd > 0 && b2) {
    spd -= 5;
  }


  //change direction if button 0 is pressed
  if (b0) {
    dir = !dir;
  }


  //control motor
  digitalWrite(DIR, dir);  //set direction
  analogWrite(EN, spd);  //Use PWM to control the motor speed


  //display data
  Serial.print("Motor speed: ");
  Serial.print(map(spd, 0, 255, 0, 100));  //convert pwm to percentage
  Serial.println("%");
  Serial.print("Direction: ");
  if (dir) {
    Serial.println("counter-clockwise");
  }
  else {
    Serial.println("clockwise");
  }


  delay(100);
}

The direction and the speed of the motor are displayed in the serial monitor.

24 Sep 2020

How to use external trigger in Digilent Test & Measurement Devices

alexwonglik1

All of Digilent Portable Test and Measurement Devices including Analog Discovery 2Analog Discovery 2, Analog Discovery StudioAnalog Discovery Studio and Digital DiscoveryDigital Discovery have external trigger. With triggers enabled, a dynamic waveform can be displayed as a static image. You can also capture data around or locate an infrequent event. For example, digital pulses are missing, irregular in width, or do not reach valid logic high or low levels. An external trigger uses an external signal to generate a trigger.

You can use Digilent Test and Measurement Device tutorial "Using External Triggers" to understand what trigger is and how trigger works in Digilent test and measurement device. In addition, you can learn how to use external trigger in oscilloscope and logic analyzer of Digilent test and measurement devices.

Trigger the measurement in oscilloscope with a push button
This is an example of using an analog signal to trigger the oscilloscope. When you press the push button, it will generate a trigger. The trigger point should change each time the button is pressed since no condition is set to be displayed at t=0.0 seconds

Record Digital Signals in Logic Analyzer with Automated Trigger
This is an example of using a digital signal to automatically trigger the logic analyzer. Digital input/output pins (DIO0 and DIO1) will be used to stimulate the external trigger and to provide some data to be read. A clock signal from DIO0 is used as the trigger. A random logic signal at a rate of 10kHz is generated on DIO1 which is being observed in the Logic instrument on the respective DIO1 signal line. DIO1 should update every two seconds in the Logic Analyzer with every rising edge of the clock signal from DIO0
- 2 Sep 2020
Build and Measure Signals and Systems on Electronics Explorer

alexwonglik1
The Digilent Electronics Explorer Electronics Explorer includes all of the test and measurement equipment needed to design, build, and test analog and digital circuits of all types. Built around a large solderless breadboard, the Electronics Explorer includes
1. 4-channel, 40MS/s, 100MHz, Oscilloscopes
2. 2-channel, 40MS/s, 20MHz, Arbitrary Waveform Generator
3. 32 digital signals that can be configured as:
  32-channel logic analyzer
  32-channel pattern generator
  Discrete digital I/Os (buttons, switches, LEDs, etc.)
4. 2-channel, ± 9V, 1.5A, variable power supply
5. 1-channel, 3.3/5V, 2A, fixed power supply
6. 4-channel voltmeter
7. 2 programmable reference voltages
8. Can connect all instruments to circuits built on the solderless breadboard using simple jumper wires
9. Come with a starter kit with the below active and passive components
Create a RC circuit and look at different input responses

You will use the Arbitrary Waveform Generator (AWG) and Oscilloscope instruments within the Digilent WaveForms software. The circuit is built on the breadboard of Electronics Explorer. The AWG will be used to apply either a step input or sinusoidal input to the RC circuit. The Oscilloscope will be used to observe the circuit’s resulting behavior. In this project, we will look at generating a step response and a sinusoidal response in the time domain. We will also use the Network Analyzer to generate a sinusoidal response in the frequency domain.

Digilent WaveForms is our powerful multi-instrument software application. It seamlessly connects to our USB portable oscilloscope, logic analyzer, and function generator products such as the Electronics Explorer, with full Windows, Mac OS X, and Linux support. Designed with a clean, easy to use graphical interface for each instrument, WaveForms makes it easy to acquire, visualize, store, analyze, produce, and reuse analog and digital signals.

Step 1: Turn on Electronics Explorer and Connect it to the computer
Connect the Electronics Explorer to your PC with the USB cable. Connect the board's external power supply and flip the Ready switch to the ON position.

Step 2: Create a simple RC circuit on the breadboard
Build the circuit by connecting the DC channel on Scope 1 to AWG channel 1, the 1 kΩ resistor from AWG channel 1 to one side of the 4.7 nF capacitor, the DC channel on Scope 2 to the same row as the connected resistor and capacitor, and by wiring the unconnected side of the capacitor to ground.

Step 3: Connect the Electronics Explorer to Waveforms
Launch the WaveForms Software. The Device Manager will pop up. Click your EExplorer on the list and click Select. The WaveForms main window will now appear.

After you build the circuit and connect them to right instruments of Electronics Explorer. We can see different input responses.

Step Response in the Time Domain
You are going to configure the Arbitrary Waveform Generator and Oscilloscope.

Configure the AWG with the following settings:
- Step input
- Frequency = 1 kHz
- Amplitude = 5V
- Offset = 5V
- Type = Square
Configure the Oscilloscope with the following settings:
- Trigger Settings: Mode to Auto, Source as Channel 1, Trigger Cond. as Falling, Trigger Level to 5V
- On the right side of the screen, set Time Position = 20us
- Time Base = 5 μs/div
- Channel 1 & 2 Offsets to -6V by typing the values in
- Channel 1 & 2 Ranges to 2V/div
- Disable Channels 3 & 4 by clicking their respective check-boxes.
Go back to the AWG window and click either the Run or Run or the green arrow on the Wavegen tab to start the AWG. Return to the Oscilloscope Window and click Run here as well. The result is shown in the figure below.

Sinusoidal Response in the Time Domain

For this portion of the project, you will use the same circuit as the previous part. You will begin by making some quick changes to the AWG and Oscilloscope instruments. Return to the AWG window and apply the following settings:
- Type = Sine
- Frequency = 20kHz
- Amplitude = 8V
- Offset = 0V
Next, you need to configure the Oscilloscope. Trigger Settings: Mode to Auto, Source as Channel 1, Trigger Cond. as Rising, Trigger Level to 5V. On the right side of the screen, set Time Position = 0s, Time Base = 10us/div, Channel 1 & 2 Offsets to 0V, Channel 1 & 2 Ranges to 2V/div. Disable Channels 3 & 4 by clicking their respective check-boxes. Go back to the AWG window and click Run AWG 1 or Run All. Return to the Oscilloscope Window and click Run here as well.

Sinusoidal Response in the Frequency Domain
Again, you will continue using the same circuit for the last portion of this project. Return to the WaveForms main window. Click the Network icon to open the Network Analyzer. Set the Start frequency to 1kHz, the Stop frequency to 230kHz, Amplitude to 5V, and Samples to 100. On the right-hand side of the WaveForms GUI, in the Magnitude box set the Top to 10dB and the Range to 30dB, and set the Channel 1 Gain to 2X. Once you have the Network Analyzer configured, click “Run”.
You should see the results shown below.

Get all the project details and explore additional features of the WaveForms software by visiting the Digilent Wiki Page.
- 4 Aug 2020
Bluetooth controlled FPGA Based Synthesizer

alexwonglik1
A student creates a Bluetooth controlled synthesizer with Digilent Nexys Video Digilent Nexys Video and Pmod BT2Pmod BT2. You can control the frequency and amplitude of 10 sine waves from the mobile apps.

Signal Processing for the Synthesizer
The synthesizer is designed in additive synthesis. This involves the summation of multiple sinusoidal signals to form a more complex signal. The additive synthesis parameters in a discrete-time implementation can be determined using the Fast Fourier Transform (FFT) that computes the Discrete Fourier Transform (DFT) of a sequence.

System Design
The system consists of
1. Microblaze Processor - soft processor controls the data flow (FFT, DMA channel to codec, memory, Bluetooh, additive generator ceofficients)
2. DDR3 Memory
3. Audio Codec driven by custom IP (with central DMA channel and 512 samples FIFOs [L and R audio channels])
4. Xilinx FFT IP with FIFO
5. Bluetooth UART
6. Additive Generator - Run the additive synthesis
Additive Synthesis Implementation
The student built a few IPs in Xilinx Vivado to run the additive synthesis. You can see the building blocks in the below block diagram.
- AXI Memory-Mapped - block provided by Xilinx, allows Microblaze processor to access IP memory, which stores data about the sound pitch, amplitude(k), phase shift(k), where k is an index of the sine wave.
- Phase generator - computes phase value based on sound pitch, phase shift, and previous phase value.
- Data generator - provides signal flow to DDS Compiler
- DDS Compiler - Xilinx IP, stores sine wavetable in Block RAM. Input : 16 bit phase value, output : 16 bit sine wave value.
- Amplitude Multiplier - perform equation A * sin[n], where A is (0 ; 1) (16 bit fraction value).
- Mixer - adds all of the sine waves.
- Normalize - multiply output by a factor based on the count of the sine waves (provides full-scale output)
Putting everything together

After you complete the block design and generate the wrapper. You can run the synthesis, implementation and export the hardware to Xilinx SDK. Then, you can write the application in C programming language. Then, you can program the design in the FPGA.

After that, you can plug in Pmod BT2 and headphone on the Nexys Video.
You also need to download the mobile apps and pair that with the Pmod BT2. Then, you can create different sounds

You can follow the steps in the project page and replicate the project.

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- 31 Jul 2020
Debug your embedded design. Look at the Xilinx Zynq boot sequence

alexwonglik1
In the process of developing a new Xilinx Zynq SoC system, it's important to know the specifications of the hardware and see the timing of signals. Unfortunately, the speed of the QSPI transactions in the boot sequence isn’t always an evident specification. Digilent Digital DiscoveryDigital Discovery and High Speed Adapter High Speed Adapter system is capable of visualizing QSPI transmission which can take place at much higher clock speeds, over 100 MHz. Because of the 512 MB DDR memory that the Digital Discovery has, it can perform very large acquisitions. Then, engineers and developers can visualize the boot sequence to determine timing.

The Digital Discovery is a USB Logic Analyzer, Protocol Analyzer and Pattern Generator. The digital inputs and outputs can be connected to a circuit using simple wire probes or breadboard wires. Alternatively, the Digital Discovery High Speed Adapter and impedance-matched probes can be used to connect and utilize the inputs and outputs for more advanced project.

Driven by the free WaveForms software application, Digital Discovery can be configured to be the following instruments:
1. 24-channel digital logic analyzer (1.2…3.3V CMOS, up to 800MS/s (with the High Speed Adapter))
2. 16-channel pattern generator (1.2…3.3V CMOS, 100MS/s)
3. 16-channel virtual digital I/O including buttons, switches, and LEDs – perfect for logic training applications
4. Digital Bus Analyzers (SPI, I²C, UART, I2S, CAN, Parallel)
5. A programmable power supply of 1.2…3.3V/100mA. The same voltage supplies the Logic Analyzer input buffers and the Pattern Generator input/output buffers, for keeping the logic level compatibility with the circuit under test.
We can look at the boot sequence of the flash on Digilent ZYBO Zynq SoC platform. First of all, you need to use SOIC clip to bring the QSPI signals out and feed them into Logic Analyzer of Digital Discovery.

Then, you can use javascript to create the debugging test and translate the signals into data in WaveForms. This can be done by choosing Click to Add Channels -> Custom in the Logic Analyzer.
```
// rgData: input, raw digital sample array
// rgValue: output, decoded data array
// rgFlag: output, decoded flag array

var c = rgData.length // c = number of raw samples
var pClock = false; // previous *** signal level
var iStart = 0; // used to keep track on word start index
var cByte = 0; // byte count per transmission
var cBits = 0; // bit counter
var bValue = 0; // value variable
var fCmd = true;

for(var i = 0; i < c; i++){ // for each sample
  var s = rgData[i]; // current sample
  var fSelect = 1&(s>>0); // pin0 is the select signal
  var fClock = 1&(s>>1); // pin1 is the clock signal
  var fData = 1&(s>>2); // pin2 is the data signal
  var fData4 = 0xF&(s>>2); // DIN 2-5 DQ 0-3
   
  if(fSelect != 0){ // select active low
  // while select inactive reset our counters/variables
  iStart = i+1; // select might become active with next sample
  cByte = 0;
  cBits = 0;
  bValue = 0;
  pClock = false;
  fCmd = true;
  continue;
  }
  if(pClock == 0 && fClock != 0){ // sample on clock rising edge

  bValue <<= 4; // serial data bit, MSBit first
  bValue |= fData4;
   
  cBits++;
  if(cBits==2){ // when got the 8th bit of the word store it
  cByte++;
  // store rgValue/Flag from word start index to current sample position
  for(var j = iStart; j < i; j++){
  // Flag change will be visible on plot even when data remains constant.
  // This is useful in case we get more consecutive equal values.
  rgFlag[j] = cByte;
  rgValue[j] = bValue;
  }
  iStart = i+1; // next word might start after this sample
  cBits = 0; // reset bit count for the next byte
  bValue = 0; // reset value variable
  }
   
  }
  pClock = fClock; // previous clock level
}
```
Once you turn on Digilent ZYBO, the instructions will be sent from Zynq to the flash memory. You can then visualize the boot sequence in the Logic Analyzer. The application note is available at Digilent Wiki.
- 1 Jul 2020
Implement Fast Fourier Transform on Xilinx Zynq SoC

alexwonglik1
The Fourier transform (FT) decomposes a signal into its constituent frequencies and shows that any signal can be re-written as the sum of sinusoidal functions. It is also a mathematical method for transforming a function of time into a function of frequency , i.e. transforming from the time domain to the frequency domain. The Fast Fourier transform (FFT) computes the Discrete Fourier transform (DFT) of a sequence.

Field Programmable Gate Arrays (FPGAs) offer a high performance and flexibility for real time implementation. FPGA is attractive for high-speed signal processing due to their parallel processing abilities. Pablo has explained how to use the Xilinx FFT IP core to offload the FFT algorithm on the Digilent Eclypse Z7 Zynq SoC PlatformDigilent Eclypse Z7 Zynq SoC Platform. He creates harmonics through FFT.

First of all, you need to add xFFT from the IP catalog.

Then, you can configure the IP by
1. Setting the number of channels and number of samples,
2. Choosing FFT algorithm.
3. Scaling options
4. Data format
5. Output ordering
Once the xFFT IP is configured, you can implement the harmonics design. The below block diagram shows Pablo's design. Other than the xFFT IP, he uses AXI-Datamover and AXI-FIFO for data storage and transfer. The input is stored in the first BRAM and then transferred to FPGA through UART.

Pablo design's block diagram (source: https://www.controlpaths.com/2020/05/25/eclypse-z7-and-xfft/ )

The project details is at Pablo's controlpath blog. He welcomes questions and feedback.
- 15 Jun 2020
Introducing Digilent Zmods: Cost-effective high-speed I/O expansion modules for FPGA boards

alexwonglik1
Many engineers have come across Digilent Pmods standard and even included Pmods in their systems. Pmod modules allow for more effective designs by routing analog signals and power supplies only where they are needed, and away from digital controller boards. However, Pmods aren't for high speed communication. So, engineers can't use Pmods in high speed instrumentation systems or digital signal processing applications. At the same time, high speed FPGA Mezzanine Cards are bulky and comparatively pricey. To solve this problem, Digilent makes use of SYZYGY standard and launch a new line of expansion modules for high-speed control, signal processing, or test and measurement applications

SYZYGY Open Source Standard

Similar to Pmod standard, SYZYGY is an open standard from Portland, Oregon’s Opal Kelly. It fits – in cost, size, and performance – somewhere between the Pmod and FMC standards. Although not much larger than many Pmods, SYZYGY-compatible modules are capable of high-bandwidth connections to an FPGA, enabling very compact and cost-effective high performance I/O. The small, SYZYGY standard form factor recommends them for compact, configurable, rugged systems.

Comparison between Pmod, Syzygy and FMC standard. Source: https://syzygyfpga.io/

Digilent Zmods

Digilent starts the Zmods line with two data acquisition Zmods - Zmod ADCZmod ADC and Zmod DACZmod DAC. The SYZYGY compatible connectors provide enough data transfer bandwidth (BW) for dual-channel, 100MSPS. The high BW and sampling rate, the flexible input/output range, the high resolution and the flexibility provided by the FPGA interface make them ideal for a wide variety of applications.

Zmod ADC 1410

Zmod DAC 1411

A pair of Zmod DAC / Zmod ADC, together with a SYZYGY compatible FPGA carrier, like Eclypse Z7Eclypse Z7, could be used for closed analog loops with digital control, digital filters with analog input and output, hardware-in-the-loop, digital signal processing, high frequency modulators/demodulators, real-time image processing, SDR, etc.

Eclypse Z7 + Zmod ADC + Zmod DAC
Zmods Support Materials

The following tutorials step through the process of creating a hardware platform that supports Zmods.
Digilent provides a set of libraries supporting Zmod modules on both Linux and baremetal (standalone) platforms. The Zmod Base Library implements functionality common to all Zmods. For each Zmod, separate libraries are implemented, based on Zmod Base Library.
- 2 Jun 2020
An in-depth look into Genesys ZU-3EG, a versatile Zynq Ultrascale+ MPSoC EG Platform

alexwonglik1
Digilent Genesys ZU-3EG is an advanced computing platform loaded with Xilinx Zynq Ultrascale+ MPSoC EG and a range of peripherals and interface. Let's take a closer look.

Memory
Main memory is a single-slot populated DDR4 SODIMM, always upgradeable by the user. It is wired to the Processing System (PS) side using the hard-core memory controller. The bundled module is a 4GiB Kingston HyperX HX424S14IB/4. There is also a serial flash memory from ISSI. This memory is used to provide non-volatile code and data storage. It can be used to initialize the PS subsystem as well as configure the Programmable Logic (PL). The flash memory is also commonly used to store non-configuration data needed by the application. If doing this from a bare-metal application, the flash memory can be freely accessed using standalone libraries included with a Xilinx SDK BSP project. If doing this from a Petalinux generated embedded Linux system, the flash can be partitioned as desired and mounted like a standard Memory Technology Device (MTD) block device. The microSD connector has a hinge-based mechanism. It is compatible with UHS-I allowing 1.8V signaling and speeds up to SDR104, or 104MB/s.

Platform MCU
Tying all the features of the Genesys ZU together into a computing platform requires an embedded controller which is called Platform MCU. Part of the platform is the coin battery, the fan, a temperature sensor inside the Zynq Ultrascale+ MPSoC EG device and Power Management Units (PMU). Management is done through dedicated signals or over the main I2C bus. The Platform MCU is implemented by a Microchip ATmega328PB. It is on the auxiliary 3.3V power domain, immediately available after power-up. This power domain is independent of the PMUs which provide main power, giving the Platform MCU control over main power. It also shares the main I2C bus with the Zynq Ultrascale+ MPSoC EG device, giving it access to all the critical peripherals. Other features include Zynq Ultrascale+ MPSoC EG device temperature sensing, fan speed control, and VADJ voltage setting. The Platform MCU program memory has two sections:
- Application where the firmware resides
- Bootloader where the bootloader resides.
Software Support
Digilent provides an out-of-the-box Petalinux project and Vivado Webpack project. There are free IP-support for the following peripherals
1. DDR4 memory controller
2. MIPI CSI-2
3. DisplayPort controller
4. Ethernet 1G
5. USB 2.0/3.0
6. PCIe Root/Mini PCIe
7. SATA/mSATA
8. On-board Wi-Fi/SPI controller
Network Interface
1. 1G Ethernet
The Genesys ZU uses a TI DP83867CR PHY to implement a 10/100/1000 Ethernet port for wired connectivity. After power-up, the PHY starts with Auto Negotiation enabled, advertising 10/100/1000 link speeds and full duplex. If there is an Ethernet-capable partner connected, the PHY automatically establishes a link with it, even with the Zynq Ultrascale+ MPSoC device is not configured.
1. Wi-Fi
Microchip ATWINC1500 module provides 2.4GHz IEEE 802.11 b/g/n wireless network connectivity. It interfaces to the PS-side of Zynq Ultrascale+ MPSoC EG device over SPI, supporting a maximum theoretical data rate of 48Mbps. The module can be used in bare-metal applications with the full IP stack included in the firmware loaded from flash. It is also supported in Linux in the ATWILC1000-compatible mode, where the firmware is loaded on-the-fly upon boot and the OS IP stack is used.
1. WLAN, Bluetooth, WWAN
The Mini PCIe socket allows users to connect any wireless radio module compatible with the PCIe Mini Card standard. With both PCIe x1 and USB 2.0 available in the socket, the dual Wi-Fi/Bluetooth modules can be used. User can use the SIM slot to bring in WWAN radio on board.

USB Interface
1. USB Full-Featured Type-C
USB 3.1 Gen1 and USB 2.0 support is handled by the Full-Featured Type-C receptacle. The connector has a USB 2.0 pair for backward compatibility, one high-speed transceiver lane (two pairs) for USB 3.1, and configuration channel (CC). Since the plug is reversible, the upper and lower rows double the number of pins for each function, designated by suffixes 1 and 2. Plug orientation is established during the configuration process over the CC1 and CC2 pins. Depending on the orientation, either pins with suffix 1 or pins with suffix 2 carry actual signals. Multiplexing 1 and 2 for the USB 3.1 lane is done by an on-board hardware multiplexer.
1. USB 2.0 Host
Host-only USB 2.0 functionality is implemented by a Microchip USB3320 PHY and a Microchip USB2513B hub. The PHY is wired to the PS-side controller of Zynq Ultrascale+ MPSoC EG device over ULPI. The hub has three Downstream-Facing Ports. Two of these connect to a dual-stacked Type-A connector, providing 0.5A current per port. The third port is connected to the MiniPCIe slot, an embedded USB port.
1. USB 2.0 - JTAG/Serial Bridge
The micro Type-B connector connects to an FTDI FT4232HQ USB bridge. It provides a JTAG interface for programming and debugging, one UART interface connected to the Zynq Ultrascale+ MPSoC EG device and one UART interface connected to the Platform MCU. The UART interfaces are exposed as standard COM ports.

Multimedia
1. DisplayPort
The dual-lane mini DisplayPort connector is wired to a PS-side DisplayPort Controller of Zynq Ultrascale+ MPSoC EG device via two PS-GTR transceiver lanes. Resolutions up to 4Kx2K@30fps are supported at a maximum 5.4Gbps line rate.
1. Audio Codec
The Genesys ZU-3EG includes an Analog Devices ADAU1761 SigmaDSP audio codec complementing its multimedia features. Four 1/8” (3.5mm) audio jacks are available for line-out, headphone-out, line-in, and microphone-in. Line-out, headphone-out and line-in jacks are stereo and the microphone input is mono. To record or play back audio, the audio data needs to be converted. The audio codec bridges the gap between the analog jacks and the digital FPGA pins. It connects to the PL side of the Zynq Ultrasacle+ MPSoC EG device. Analog-to-digital and digital-to-analog conversion is done at up to 24 bits and 96 kHz sampling rate. Digital audio data is carried to/from the FPGA on a serial, full-duplex interface, which supports several different formats, the default being I2S. This interface is clocked by the FPGA through BCLK by default, but the codec can be configured to provide the clock itself. Configuring the audio codec can be done over I2C. The codec is clocked from the FPGA through the Master Clock (MCLK) pin. A clock must be provided for the codec to function, including the I2C port. The exact frequency depends on the desired sample rate and whether PLL will be used, but 12 MHz is a good start.
1. MIPI ports
The two MIPI ports are 15-pin, 1 mm pitch, zero insertion force (ZIF) connectors designed specifically for attaching Digilent PCAM 5C, 5MP camera sensor modules, to Genesys ZU-3EG. It allows for bi-directional D-PHY lanes thanks to direct I/O support in the UltraScale+ architecture. Therefore, it also supports MIPI DSI applications.

Mini PCIe / mSATA
It is compatible with PCI Express Mini card types F1/F2 (Full-Mini) and H1/H2 (Half-Mini) and mSATA card types Mini and Full size. Mechanical compatibility is assured by the relocatable stand-offs included in Genesys ZU-3EG. Electrically, the SATA lane and the PCIe x1 lane share the same PS-GTR transceiver lane. Therefore, it is up to the MPSoC configuration to enable either the SATA or the PCIe Root controller and map it to the GTR lane. Mini PCIe modules can also make use of the embedded USB 2.0 port wired to the on-board USB hub and the MPSoC USB1 controller up the chain.

Expansion Port
1. Low-Pin Count FMC Connector
The Genesys ZU includes an FPGA Mezzanine Card (FMC) Standard-conforming carrier card connector that enables connecting mezzanine modules compliant with the same standard. All user defined signals are bonded to the PL-side of the Zynq Ultrascale+ MPSoC EG device.
1. Zmod
The Zmod port uses the SYZYGY Standard interface to communicate with installed SYZYGY pods. Each SYZYGY Standard interface contains 14 single-ended I/O pins (2 of which I2C), 8 differential I/O pairs (which can alternatively be used as 16 additional single-ended I/O pins), and two dedicated differential clocks - one for input and one for output. The Zmod port is wired to PL-side Zynq Ultrascale+ MPSoC EG device powered by the VADJ rail, sharing them with FMC signals.
1. Pmod
Pmod ports are 2×6, right-angle, 100-mil spaced female connectors that mate with standard 2×6 pin headers. Each 12-pin Pmod port provides two 3.3V VCC signals (pins 6 and 12), two Ground signals (pins 5 and 11), and eight logic signals

Oscillators
The PS on Genesys ZU-3EG has a clock source of 30MHz while the PL has a clock source of (by default) 25MHz

Coin battery
A Seiko TS621E lithium rechargeable battery provides power to the Zynq Ultrascale+ MPSoC EG device Battery Power Domain (BPD) through the VCC_PSBATT pin. It is connected in parallel with a 100 uF capacitor. The BPD includes the real-time clock with a dedicated crystal oscillator and a RAM available for storing a secure configuration key. The capacitor alone can provide power for approx. 15 minutes after main power is turned off. The battery will provide power after that.

You can have the detailed information from Genesys ZU-3EG reference manual
- 19 May 2020