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Embedded and Microcontrollers
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Embedded and Microcontrollers
Blog PSoC 6 and ModusToolbox: Create a FreeRTOS 10.3 Project
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  • Author Author: Jan Cumps
  • Date Created: 27 Feb 2021 11:03 AM Date Created
  • Views 2918 views
  • Likes 11 likes
  • Comments 11 comments
  • infineon
  • modustoolbox
  • psoc 6
  • psoc_6
  • psoc6
  • freertos
  • cypress
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PSoC 6 and ModusToolbox: Create a FreeRTOS 10.3 Project

Jan Cumps
Jan Cumps
27 Feb 2021

The steps to create an empty PSoC 6 project and run FreeRTOS on the CM4 core.

image

 

It's easy to set up a FreeRTOS project in ModusToolbox. The simplest way is to start from one of the examples of the IDE's Application Creator.

But adding FreeRTOS to a project is straightforward too. And it allows you to select the newest version. In my case 10.3.

 

Start an empty project

File > New > ModusToolbox Application

image

Select the PSoC empty project for your board:

image

I use the WiFi BT prototyping kit, so I selected that one. Press Next.

Look up and select the empty project. Rename it (I used PSoC6_FreeRTOS_10_3). Press Create.

image

Once the wizard generated the project, press Close and return to the IDE.

 

Add FreeRTOS 10.3

 

With the project active, select the Library Manager in the Quick Panel.

image

 

On the Libraries tab, select freertos, shared, and version 10.3.1 release (or the version you want to use).

image

Click Update, then Close when finished. Return to the IDE.

 

Then, add a FreeRTOSConfig.h file to your project. You do that by copying the one from the shared FreeRTOS area into your project:

image

 

Paste this in the root of your project.

Then open that copied file, and remove the "#warning This is a template. Copy this file to your project and remove this line" line.

 

As last step in the preparation, add this to the include section of your main.c file:

 

#include "FreeRTOS.h"

 

Edit the Make file

 

Now a step that was not needed for the rtos version 10.1xxx. But if you don't do it for 10.3, your build will fail:

Open the Makefile by double-clicking it. You find it in the root of your project.

Update the COMPONENTS section:

 

COMPONENTS=FREERTOS

 

image

 

Now that we are in the make file, let's also change the name of the output file. It's called mtb-example-psoc6-empty-app by default. See the orange part of the image above.

 

APPNAME=mtb-example-psoc6-freertos-10-3-app

 

When you change the output file name, you need to update the execution configuration.

You do that by, after saving the make file,  clicking the Generate Launches option in the Quick Panel. See the blue part in the image.

 

This is a good time to do a first build. If it succeeds, you know you have a good start.

 

Add a Task and Start FreeRTOS

 

We're going to make a blinky (I tried to keep that a secret until the end of the post image ).

Our project will have one FreeRTOS task that will toggle the led every time it's activated by the scheduler.

 

The Task

 

I will discuss the task first, and then the activities to configure the LED and schedule the task.

 

void task_blink(void* param) {
  /* Suppress warning for unused parameter */
  (void) param;

  /* Repeatedly running part of the task */
  for (;;) {
    cyhal_gpio_toggle(CYBSP_USER_LED);
    vTaskDelay(pdMS_TO_TICKS(1000));
  }
}

 

The task is very simple. A LED is toggled, and the task yields to the RTOS scheduler for one second. In an ever lasting loop.

The effect is that the led will blink every 2 seconds:

  • LED toggle
  • yield for a second

During the Delay, the task is inactive and the scheduler can execute other tasks.

This is different to delay mechanisms that use MCU ticks to burn time. Those occupy the MCU for a second. The FreeRTOS vTaskDelay() task frees the MCU for a second.

 

I've put the task in a separate header and source file:

 

task_blink.h

#ifndef SOURCE_TASK_BLINK_H_
#define SOURCE_TASK_BLINK_H_

#include "FreeRTOS.h"
#include "task.h"

void task_blink(void* param);

#endif /* SOURCE_TASK_BLINK_H_ */

 

task_blink.c

#include "cybsp.h"
#include "cyhal.h"
#include "FreeRTOS.h"
#include "cycfg.h"
#include "task_blink.h"

void task_blink(void* param) {
  /* Suppress warning for unused parameter */
  (void) param;

  /* Repeatedly running part of the task */
  for (;;) {
    cyhal_gpio_toggle(CYBSP_USER_LED);
    vTaskDelay(pdMS_TO_TICKS(1000));
  }
}

 

The Scheduler

 

In the main() function, create and register the task, then start the scheduler:

 

  xTaskCreate(task_blink, "blink task", configMINIMAL_STACK_SIZE,
    NULL, configMAX_PRIORITIES - 7, NULL);

  vTaskStartScheduler();
  /* RTOS scheduler exited */
  /* Halt the CPU if scheduler exits */
  CY_ASSERT(0);

  for (;;) {
  }

 

The first call registers our task. The constants in the parameters are defined in the FreeRTOSConfig.h file you placed in the project root.

Then the scheduler is started. In a FreeRTOS project, this call is going to be active forever. Any line of code below that should never run.

 

The last thing to discuss here is that the hardware has to be initialised before it will be used. In our case, the LED:

 

    /* Initialize the User LED */
    result = cyhal_gpio_init(CYBSP_USER_LED, CYHAL_GPIO_DIR_OUTPUT,
                             CYHAL_GPIO_DRIVE_STRONG, CYBSP_LED_STATE_OFF);

    /* GPIO init failed. Stop program execution */
    if (result != CY_RSLT_SUCCESS)     {
        CY_ASSERT(0);
    }

 

You may have to adapt this (and the task) to use an LED that's available on your board. I think that CYBSP_USER_LED is available on all evaluation kits, but I'm not sure.

 

main.c

#include "cy_pdl.h"
#include "cyhal.h"
#include "cybsp.h"

#include "FreeRTOS.h"
#include "task.h"

#include "task_blink.h"

int main(void) {
  cy_rslt_t result;

  /* Initialize the device and board peripherals */
  result = cybsp_init();
  if (result != CY_RSLT_SUCCESS) {
    CY_ASSERT(0);
  }

  /* Initialize the User LED */
  result = cyhal_gpio_init(CYBSP_USER_LED, CYHAL_GPIO_DIR_OUTPUT,
      CYHAL_GPIO_DRIVE_STRONG, CYBSP_LED_STATE_OFF);

  /* GPIO init failed. Stop program execution */
  if (result != CY_RSLT_SUCCESS) {
    CY_ASSERT(0);
  }

  __enable_irq();

  xTaskCreate(task_blink, "blink task", configMINIMAL_STACK_SIZE,
    NULL, configMAX_PRIORITIES - 7, NULL);

  vTaskStartScheduler();
  /* RTOS scheduler exited */
  /* Halt the CPU if scheduler exits */
  CY_ASSERT(0);

  for (;;) {
  }
}

 

This is it. Build the project, then execute it on your board.

The end result is a blinking LED.

 

The project I used for this post is attached.

 

PSoC 6 series
Create a Project with its own Board- and Module configurations
Low Power Management - prepare the board for current measurements
Power consumption without WiFi or Bluetooth
Create a FreeRTOS 10.3 Project
UART receiver with FreeRTOS
FreeRTOS message queue
UART receiver with FreeRTOS - Deep Sleep support
Attachments:
PSoC6_FreeRTOS_1_3.zip
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Top Comments

  • Jan Cumps
    Jan Cumps over 2 years ago in reply to DAB +4
    Can you please stop rating my posts DAB? They are at the bottom of the e14 ratings because you tag a 3 star to virtually all of them. When I have a 5 star post on e14 with a typo, I don't fix the typo…
  • genebren
    genebren over 2 years ago +2
    Very nice write up on this FreeRTOS project. I had used FreeRTOS years ago, but I keep thinking that this is something that I need to re-learn and use in some of my projects. Thanks for the info!
  • Jan Cumps
    Jan Cumps over 2 years ago in reply to genebren +2
    It hasn't changed that much. The number of supported controllers has increased significantly. But if you used it years ago, the same mechanisms still apply: - tasks - schedules - semaphores - queues and…
  • Jan Cumps
    Jan Cumps 2 months ago in reply to cjh39

    I don't know. If you have a kit from Infineon, and their example doesn't work for you in ModusToolbox,
    it may be good to ask on their support forum.

    I wouldn't try anything custom yet, before the out-of-box experience works.

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  • cjh39
    cjh39 2 months ago in reply to cjh39

    Im not sure if we need to modify any config files on Modus/CYC8KIT ?

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  • cjh39
    cjh39 2 months ago in reply to Jan Cumps

    Not on the CY8CKIT-064S0S2-4343W .

    On the PSoC6 WiFi BT Prototyping Board the debugging works, and we can step through the program.

    Is there something specific we have to do on the CY8CKIT-064S0S2-4343W to get to work in Debug mode ?

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  • Jan Cumps
    Jan Cumps 2 months ago in reply to cjh39

    Are you able to debug any of the default ModusToolbox examples from Infineon?

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  • cjh39
    cjh39 2 months ago

    Hello,

    We have built the application successfully, but when we try to run it in debug it is instantly going to

    imageimage

    It appears to be running in Modus, but we are unable to step the program or confirm if it is actually running.

    Please let us know Jan Cumps .

    Attached is our build output.

    Started by GNU MCU Eclipse
    Open On-Chip Debugger 0.11.0+dev-4.4.0.2134 (2022-09-08-13:07)
    Licensed under GNU GPL v2
    For bug reports, read
    	http://openocd.org/doc/doxygen/bugs.html
    kitprog3 set_latest_version: C:/Infineon/Tools/ModusToolbox/tools_3.0/fw-loader 2.40.1241
    ** Main Flash size limited to 0x1D0000 bytes
    adapter speed: 2000 kHz
    adapter srst delay: 0
    adapter srst pulse_width: 5
    ** Using POWERUP_DELAY: 5000 ms
    ** Using TARGET_AP: cm4_ap
    ** Using ACQUIRE_TIMEOUT: 15000 ms
    ** Auto-acquire enabled, use "set ENABLE_ACQUIRE 0" to disable
    Info : Using CMSIS-flash algorithms 'CY8C6xxA_SMIF_S25FL512S' for bank 'psoc64_smif_cm4' (footprint 12780 bytes)
    Info : CMSIS-flash: ELF path: ../flm/cypress/cat1a/CY8C6xxA_SMIF_S25FL512S.FLM
    Info : CMSIS-flash: Address range:     0x18000000-0x1BFFFFFF
    Info : CMSIS-flash: Program page size: 0x00001000 bytes
    Info : CMSIS-flash: Erase sector size: 0x00040000 bytes, unified
    srst_only separate srst_gates_jtag srst_open_drain connect_deassert_srst
    Warn : SFlash programming allowed for regions: USER, TOC, KEY
    Info : CMSIS-DAP: SWD supported
    Info : CMSIS-DAP: Atomic commands supported
    Info : CMSIS-DAP: FW Version = 1.2.0
    Info : CMSIS-DAP: Interface Initialised (SWD)
    Info : SWCLK/TCK = 1 SWDIO/TMS = 1 TDI = 0 TDO = 0 nTRST = 0 nRESET = 1
    Info : CMSIS-DAP: Interface ready
    Info : KitProg3: FW version: 2.40.1241
    Info : VTarget = 2.507 V
    Info : kitprog3: acquiring the device (mode: reset)...
    Info : clock speed 2000 kHz
    Info : SWD DPIDR 0x6ba02477
    ***************************************
    ** Use overriden Main Flash size, kb: 1856
    ** Silicon: 0xE4A0, Family: 0x102, Rev.: 0x12 (A1)
    ** Detected Device: CYS0644ABZI-S2D44
    ** Flash Boot version: 4.0.2.1842
    ** SFlash version: 0x4bbb0
    ***************************************
    Info : gdb port disabled
    Info : starting gdb server for psoc64.cpu.cm4 on 3333
    Info : Listening on port 3333 for gdb connections
    Info : Deferring arp_examine of psoc64.cpu.cm4
    Info : Use arp_examine command to examine it manually!
    Error: [psoc64.cpu.cm4] Target not examined, will not halt after reset!
    Info : SWD DPIDR 0x6ba02477
    Info : kitprog3: acquiring the device (mode: reset)...
    Info : Waiting up to 15.0 sec for the bootloader to open AP #2...
    Info : Waiting up to 15.0 sec for the handshake from the target...
    Info : [psoc64.cpu.cm4] external reset detected
    psoc64.cpu.cm4 halted due to debug-request, current mode: Thread 
    xPSR: 0x61000000 pc: 0x1600400c msp: 00000000
    Started by GNU MCU Eclipse
    Info : Listening on port 6666 for tcl connections
    Info : Listening on port 4444 for telnet connections
    Info : accepting 'gdb' connection on tcp/3333
    Info : New GDB Connection: 1, Target psoc64.cpu.cm4, state: halted
    Warn : Prefer GDB command "target extended-remote :3333" instead of "target remote :3333"
    semihosting is enabled
    Info : Auto-detected RTOS: FreeRTOS
    Info : Auto-detected RTOS: FreeRTOS
    Info : Deferring arp_examine of psoc64.cpu.cm4
    Info : Use arp_examine command to examine it manually!
    Error: [psoc64.cpu.cm4] Target not examined, will not halt after reset!
    Info : SWD DPIDR 0x6ba02477
    Info : kitprog3: acquiring the device (mode: reset)...
    Info : Waiting up to 15.0 sec for the bootloader to open AP #2...
    Info : Waiting up to 15.0 sec for the handshake from the target...
    Info : [psoc64.cpu.cm4] external reset detected
    psoc64.cpu.cm4 halted due to debug-request, current mode: Thread 
    xPSR: 0x61000000 pc: 0x1600400c msp: 00000000, semihosting
    
    [ 32%] [##########                      ] [ Erasing     ]
    [ 36%] [###########                     ] [ Erasing     ]
    [ 39%] [############                    ] [ Erasing     ]
    [ 43%] [#############                   ] [ Erasing     ]
    [ 45%] [##############                  ] [ Erasing     ]
    [ 47%] [###############                 ] [ Erasing     ]
    [ 50%] [################                ] [ Erasing     ]
    [ 54%] [#################               ] [ Erasing     ]
    [ 58%] [##################              ] [ Erasing     ]
    [ 60%] [###################             ] [ Erasing     ]
    [ 65%] [####################            ] [ Erasing     ]
    [ 67%] [#####################           ] [ Erasing     ]
    [ 69%] [######################          ] [ Erasing     ]
    [ 73%] [#######################         ] [ Erasing     ]
    [ 78%] [########################        ] [ Erasing     ]
    [ 80%] [#########################       ] [ Erasing     ]
    [ 82%] [##########################      ] [ Erasing     ]
    [ 86%] [###########################     ] [ Erasing     ]
    [ 89%] [############################    ] [ Erasing     ]
    [ 91%] [#############################   ] [ Erasing     ]
    [ 95%] [##############################  ] [ Erasing     ]
    [100%] [################################] [ Erasing     ]
    Info : Deferring arp_examine of psoc64.cpu.cm4
    Info : Use arp_examine command to examine it manually!
    Error: [psoc64.cpu.cm4] Target not examined, will not halt after reset!
    Info : SWD DPIDR 0x6ba02477
    Info : kitprog3: acquiring the device (mode: reset)...
    Info : Waiting up to 15.0 sec for the bootloader to open AP #2...
    Info : Waiting up to 15.0 sec for the handshake from the target...
    Info : [psoc64.cpu.cm4] external reset detected
    psoc64.cpu.cm4 halted due to debug-request, current mode: Thread 
    xPSR: 0x61000000 pc: 0x1600400c msp: 00000000, semihosting
    
    [100%] [################################] [ Erasing     ]
    Info : Flash write discontinued at 0x1002c3f3, next section at 0x10050000
    Info : Padding image section 0 at 0x1002c3f3 with 13 bytes (bank write end alignment)
    
    [ 16%] [#####                           ] [ Programming ]
    [ 22%] [#######                         ] [ Programming ]
    [ 32%] [##########                      ] [ Programming ]
    [ 40%] [############                    ] [ Programming ]
    [ 49%] [###############                 ] [ Programming ]
    [ 50%] [################                ] [ Programming ]
    [ 58%] [##################              ] [ Programming ]
    [ 66%] [#####################           ] [ Programming ]
    [ 75%] [########################        ] [ Programming ]
    [ 83%] [##########################      ] [ Programming ]
    [ 93%] [#############################   ] [ Programming ]
    [ 99%] [############################### ] [ Programming ]
    [100%] [################################] [ Programming ]
    Info : Padding image section 1 at 0x10056507 with 249 bytes (bank write end alignment)
    
    [100%] [################################] [ Programming ]
    Info : Deferring arp_examine of psoc64.cpu.cm4
    Info : Use arp_examine command to examine it manually!
    Error: [psoc64.cpu.cm4] Target not examined, will not halt after reset!
    Info : SWD DPIDR 0x6ba02477
    Info : kitprog3: acquiring the device (mode: reset)...
    Info : Waiting up to 15.0 sec for the bootloader to open AP #2...
    Info : Waiting up to 15.0 sec for the handshake from the target...
    Info : [psoc64.cpu.cm4] external reset detected
    psoc64.cpu.cm4 halted due to debug-request, current mode: Thread 
    xPSR: 0x61000000 pc: 0x1600400c msp: 00000000, semihosting
    Info : SWD DPIDR 0x6ba02477
    Error: Failed to read memory at 0xfffff000
    Info : SWD DPIDR 0x6ba02477
    Error: Failed to read memory at 0xfffff000
    Info : Deferring arp_examine of psoc64.cpu.cm4
    Info : Use arp_examine command to examine it manually!
    Error: [psoc64.cpu.cm4] Target not examined, will not halt after reset!
    Info : SWD DPIDR 0x6ba02477
    Info : kitprog3: acquiring the device (mode: reset)...
    Info : Waiting up to 15.0 sec for the bootloader to open AP #2...
    Info : Waiting up to 15.0 sec for the handshake from the target...
    Info : [psoc64.cpu.cm4] external reset detected
    psoc64.cpu.cm4 halted due to debug-request, current mode: Thread 
    xPSR: 0x61000000 pc: 0x1600400c msp: 00000000, semihosting
    ===== arm v7m registers
    (0) r0 (/32): 0x40200000
    (1) r1 (/32): 0x0000000e
    (2) r2 (/32): 0x40200200
    (3) r3 (/32): 0x16004000
    (4) r4 (/32): 0x16004009
    (5) r5 (/32): 0x08007ebc
    (6) r6 (/32): 0x00000001
    (7) r7 (/32): 0xa0000000
    (8) r8 (/32): 0xfdffd6e7
    (9) r9 (/32): 0xfbffeffe
    (10) r10 (/32): 0xeffffffd
    (11) r11 (/32): 0xbdd4f7ff
    (12) r12 (/32): 0xa0000000
    (13) sp (/32): 0x00000000
    (14) lr (/32): 0xffffffff
    (15) pc (/32): 0x1600400c
    (16) xPSR (/32): 0x61000000
    (17) msp (/32): 0x00000000
    (18) psp (/32): 0xdf7ffff0
    (20) primask (/1): 0x01
    (21) basepri (/8): 0x00
    (22) faultmask (/1): 0x00
    (23) control (/3): 0x00
    (42) d0 (/64): 0x7dbfffffbfddeff7
    (43) d1 (/64): 0xffebfffbdfd7ffff
    (44) d2 (/64): 0xaa5fbdfeff7edff3
    (45) d3 (/64): 0xffefffffffeefbfb
    (46) d4 (/64): 0xfebfdfffffdffeff
    (47) d5 (/64): 0x3bdffbeffffcf7f7
    (48) d6 (/64): 0xf7fdffbdfeeffffb
    (49) d7 (/64): 0xbdfbfffff777dfff
    (50) d8 (/64): 0x6fffffffddfd66f7
    (51) d9 (/64): 0xbfffff7fefff7fe9
    (52) d10 (/64): 0xf9bfffbfffe7dfff
    (53) d11 (/64): 0xffffef5ff5afffef
    (54) d12 (/64): 0xefffffffefffffff
    (55) d13 (/64): 0xffffbefffbad7fef
    (56) d14 (/64): 0xe7fcfeff7fbffffb
    (57) d15 (/64): 0x7fbff77fff3edf7f
    (58) fpscr (/32): 0x00000000
    ===== Cortex-M DWT registers
    

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