FPGA is fun and easy to learn. Interfacing of Digilent Cmod S6 FPGA development board with 7 segment display. In this code 7 segment display is directly connected to FPGA but it can also be connected through BCD to 7 segment decoder to minimize the number of IO pins.
Cmod S6 Schematics: cmods6_sch.pdf
Master UCF file: cmod_s6_master_ucf.zip
Factory Loaded Example: cmods6_demo.zip
Reference Manual for Factory Loaded Demo: reference-manual
VHDL Syntax for Port, Mode, and Type Signal Concurrency : lecture.html
How to create MCS file using Xilinx ISE: Tutorial.pdf
VHDL reference: VHDL ref