Group Actions
Engagement
  • Author Author: mahmood.hassan
  • Date Created: Date Created
  • Views 1276 views
  • Likes 3 likes
  • Comments 2 comments
Related
Recommended

7 Segment Interfacing - Digilent Cmode S6 FPGA Board

mahmood.hassan

FPGA is fun and easy to learn. Interfacing of Digilent Cmod S6 FPGA development board with 7 segment display. In this code 7 segment display is directly connected to FPGA but it can also be connected through BCD to 7 segment decoder to minimize the number of IO pins.

 

Demo:

 

Important Links:

Cmod S6 Schematics: cmods6_sch.pdf

Master UCF file: cmod_s6_master_ucf.zip

Factory Loaded Example: cmods6_demo.zip

Reference Manual for Factory Loaded Demo: reference-manual

VHDL Syntax for Port, Mode, and Type Signal Concurrency : lecture.html

How to create MCS file using Xilinx ISE: Tutorial.pdf

VHDL reference: VHDL ref

Attachments:
blink_led.zip
Parents

  • Very cool. How much fabric (LUT's, CLB, SRAM, etc did this use?)

    Thanks

  • in reply to clem57

    Its a fairly simple design and I am working with FPGA after so many years and feeling happy that it didn't took more than few minutes to write this code.

     

    Design Summary

    Number of errors:      0

    Number of warnings:    0

    Slice Logic Utilization:

         Number of Slice Registers:                  12 out of   4,800    1%

         Number of Slice LUTs:                         12 out of   2,400    1%

         Number used as Memory:                    0 out of   1,200    0%

     

    Slice Logic Distribution:

         Number of occupied Slices                   8 out of     600    1%

         Number of fully used LUT-FF pairs:      12 out of      12  100%

         Number of unique control sets:             1

         Number of slice register sites lost

              to control set restrictions:               4 out of   4,800    1%

     

    Specific Feature Utilization:

         Number of RAMB16BWERs:                0 out of      12    0%

         Number of RAMB8BWERs:                  0 out of      24    0%

Comment
  • in reply to clem57

    Its a fairly simple design and I am working with FPGA after so many years and feeling happy that it didn't took more than few minutes to write this code.

     

    Design Summary

    Number of errors:      0

    Number of warnings:    0

    Slice Logic Utilization:

         Number of Slice Registers:                  12 out of   4,800    1%

         Number of Slice LUTs:                         12 out of   2,400    1%

         Number used as Memory:                    0 out of   1,200    0%

     

    Slice Logic Distribution:

         Number of occupied Slices                   8 out of     600    1%

         Number of fully used LUT-FF pairs:      12 out of      12  100%

         Number of unique control sets:             1

         Number of slice register sites lost

              to control set restrictions:               4 out of   4,800    1%

     

    Specific Feature Utilization:

         Number of RAMB16BWERs:                0 out of      12    0%

         Number of RAMB8BWERs:                  0 out of      24    0%

Children
No Data