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Blog 7 Ways to Leave Your Spartan-6 Challenge - external VpVn Differential Input working with XADC
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  • Author Author: ralphjy
  • Date Created: 3 Aug 2022 5:30 AM Date Created
  • Views 824 views
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  • Comments 4 comments
  • arty-s7
  • 7 Ways to Leave Your Spartan-6
  • spartan-7
  • xilinx fpga
  • Spartan_Migration
  • xadc
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7 Ways to Leave Your Spartan-6 Challenge - external VpVn Differential Input working with XADC

ralphjy
ralphjy
3 Aug 2022

Well, my challenging week is continuing.  I'm not sure whether it is bad luck, faulty hardware, or just unfortunate coincidences.

I decided to take a look at the problem that I was having with the external inputs to the XADC last night.  After some quick testing I realized that the dedicated VP/VN differential input was working, but the auxiliary inputs configured as single-ended were not.  I decided to hook a simple potentiometer to provide a variable voltage to demonstrate the working differential input before continuing to troubleshoot the aux inputs.

Yesterday my Android tablet also crashed as it was casting its display to my PC.  I had just finished recording the screencast in my previous blog and had taken a coffee break.  When I got back the screen had shut off and I could not get the tablet to turn back on.  I had to resort to a hard power cycle by holding the power and volume down buttons simultaneously for about 10 seconds.  That restarted the tablet, but I haven't been able to get the casting functioning since then.  Another problem to fix...

This morning when I went to modify the program on the Arty S7, I couldn't program the FPGA because the PC could no longer recognize the Arty USB device.  There was still power on the port, but I verified that the port was not functioning by using another cable and a known working dev board.  I decided to use a powered USB hub to connect the Arty and protect my PC from potentially further damage.  Using the hub on a working USB port has my setup working again.  Another problem to look into...  I had already tried rebooting the PC without the Arty attached, but I have not tried disabling and re-enabling all of the USB hardware to see if that helps.

Anyway, I hooked up a Grove 10k pot to the shield connector to run my test.  Here's a picture of the setup:

image

And a video showing the voltage changing between 0 to 1V on the VpVn channel.  This is still using the Serial BLE Terminal on my Android tablet.  The video looks a bit different because I am now using the free version of Vysor to do the screen mirroring to my PC.  The free version only does low resolution mirroring over USB.  I had previously been doing screencasting via WiFi.

I did 5 samples at 0V before turning the pot.  There is an initial offset of 10 to 12 mV.  The pot is only single turn, so the voltage spacing of the samples is pretty rough.  But it does show that the input does have the correct connectivity from the shield connector through the mux to the ADC.

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I have a suspicion that the problem with the aux inputs is that they are not getting configured properly as unipolar singled-ended inputs.  With all the problems that I'm having, I think that I've run out of time - so, I'll work on my project summary tomorrow.  I'm sure that when I finally figure it out - that something is just not getting set correctly in the tool.

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  • javagoza
    javagoza over 2 years ago

    image

    This is the configuration for the XADC Wizard for the Digilent´s Base system. I have built it without problems with version 2021.1 of Vivado ML

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  • javagoza
    javagoza over 2 years ago in reply to Jan Cumps

    Currently what I do is to click on the DB file in the Vivado Sources Hierarchy window and select Reset Output Products. This deletes all of the generated files for the Block Diagram.

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  • Jan Cumps
    Jan Cumps over 2 years ago in reply to javagoza

    I suspect it must be some job that sometimes gets stuck and is needed for a next step.

    This can help; if you think something has gotten out of sync:

    image

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  • javagoza
    javagoza over 2 years ago

    I'm sorry you're having so much trouble with your devices. During this program I have had several moments of frustration like this but I think I have become hooked on the program and the desire to prove to myself that I was capable of continuing has been stronger.

    With the current thermal camera project that I am trying I have begun to have problems with Vivado, the project is already very large and there are times that you have to try several times to generate the bitstream despite not making any changes at the end after several attempts it manages to generate. I suspect it must be some job that sometimes gets stuck and is needed for a next step.


    I also have had to increase the internal memory to 128K in addition to passing the data to the DDR3 memory from the linker options in Vitis. The thermal sensor and the animation on the VGA screen require a lot of memory.


    I haven't tried the XADC yet, but the project that is initially loaded on the Arty includes the configuration of the analog inputs for the Arty S7 50.

    https://github.com/Digilent/Arty-S7-50-base/releases/download/v2017.2.1-1/OoB-Demo-2017.2.1-1.zip

    Arty-S7-50-base/src/bd/system/ip/system_xadc_wiz_0_0 at master · Digilent/Arty-S7-50-base (github.com)

    Also Jan Cumps has an example of using the XADC 

    Migrate the Digilent XADC demo (to Vivado 2020.2) - Blog - FPGA - element14 Community

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