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The Art of FPGA Design - Post 3

fpgaguru

Two Free VHDL Books

 

If you installed Vivado WebPACK, the free version of Xilinx FPGA design tools, you are ready now to start creating your first hardware design. There are at least three different ways to program a Xilinx FPGA today, using a hardware description language like VHDL or Verilog/SystemVerilog, using Vivado HLS using C/C++ and Vivado SystemGenerator or ModelComposer which requires Matlab and Simulink. Each design flow has advantages and disadvantages and the third one is not free.

 

HDL languages like VHDL and Verilog are mature design languages, FPGA design in the last 20 years has been done more or less entirely using HDL flows. HLS is a much more recent design flow, it provides a higher abstraction level and faster simulation times but lower performance in terms of speed and device utilization.

 

We will start for now by using VHDL. In the 90s we had a fierce HDL language war, hardware designers debating endlessly which one is better, VHDL or Verilog? It turned out that both sides were right and the best tool is the one you know how to use. Today's HDL simulation and synthesis tools let you mix and match the two HDL languages and you can use other people's code in your design even if it is not your favorite HDL dialect.

 

This will not be a VHDL 101 style course, I will assume that you have at least a basic level knowledge of the language. If that's not the case, in the same spirit of free everything I highly recommend Peter Ashenden's 1990 "The VDHL Cookbook" - old but good, it's the book I used to learn VHDL:

https://tams.informatik.uni-hamburg.de/vhdl/doc/cookbook/VHDL-Cookbook.pdf

 

Another good resource is "Free Range VHDL, the no-frills guide to writing powerful code for your digital implementations" by Fabrizio Tappero, Bryan Mealy. You can download a free PDF copy from here:

http://freerangefactory.org/

 

Finally, not a free book but a very useful one if you want to bring your VHDL coding skills into the 21st century "VHDL 2008: Just the New Stuff" by the same Peter Ashenden and Jim Lewis, a well known VHDL expert:

https://www.amazon.com/VHDL-2008-Stuff-Systems-Silicon/dp/0123742498/ref=sr_1_1?ie=UTF8&qid=1531850195&sr=8-1&keywords=VHDL-2008+just+the+new

 

In the next few posts I will talk about VHDL coding styles and how to create efficient and high speed FPGA designs, how to write generic and reusable code, VHDL-93 vs VHDL-2008 and other similar subject matters.

 

Back to the top: The Art of FPGA Design

  • in reply to gustavovelascoh

    Hi Gustavo, nothing has changed much and I do not expect a major change in the near future either. There is a place for every design language and flow, each one has its strengths and weaknesses. The ideal would be to be able to seamlessly mix HLS and HDL blocks in the same design, we are moving in that direction but it will take time.

  • Hi Catalin, thanks for your series of posts on FPGA. I will give FPGA a try (again). On this post you mentioned that HLS design flow is good in terms of abstraction, simulation time and time to market, but poor in performance. Is this still the case today (2 years after)? Thanks

  • in reply to johnbeetem

    Yes, the HDL language wars are a thing of the past, we have moved along.

     

    If you live in Verilog land you should probably start looking into SystemVerilog. If you are trying to learn Verilog right now you should definitely give SystemVerilog a try instead and save yourself a lot of grief. It is backwards compatible and whatever you do in Verilog can also be done more or less in SystemVerilog so you do not lose anything. SystemVerilog is becoming the standard for HDL simulation and verification but a consensus seems to be emerging between Verilog users that SystemVerilog is not the perfect choice for HDL synthesis and the adoption rate is not that great. SystemVerilog is making an attempt to bridge the gap between Verilog and VHDL by borrowing the good features from the second, maybe that's why image. I am definitely not a Verilog expert so please take my opinion with a grain of salt.

     

    If you live in VHDL land then VHDL-2008 (as opposed to classic VHDL-93) is what you should aim for at this stage, both as a beginner or an experienced VHDL designer. There are significant improvements, some of them cosmetic that will make your coding life easier but some very deep additions that can help a lot with raising the level of abstraction when doing HDL designs.

     

    The first link for the 2014 post you provided is still accurate except for the point where it mentions the cost of entry into HLS design flows as $100K - in fact, with Vivado WebPack edition that cost is literally zero, so if an HLS flow (C/C++ to gates) is your cup of tea there is probably no cheaper way to program FPGAs using C/C++. The quality of results is still not the greatest and the learning curve is still quite steep but there really is no financial barrier anymore. 

     

    The second link is a very good example for the problems a beginner faces when moving from a software development background into HDL design, especially with Verilog but even VHDL can be quite frustrating at first. There is indeed a major dividing line between coding style for simulation, that you can use for example in testbenches and coding style for synthesis, which is much more restrictive. Grasping the concepts of RTL (register transfer level) design, clocks, combinatorial vs sequential logic and what is the proper coding style to describe each one is probably the greatest hurdle for a beginner, especially when they come from a software programming background. This tends to have an unintended consequence, hardware designers eventually learn the hard way how to write HDL code that is synthesizeble and then stick to a very restrictive coding style, even as they become experienced designers. The resulting code becomes a sort of netlist of very simple synthesizable constructs and enforces the view that HDLs are low level and verbose. The fact is that within the restrictions imposed by synthesizable coding style rules there is a lot of room for much more efficient, higher level of abstraction code especially with SystemVerilog and VHDL-2008.

     

    In the end, whether you like HDLs or not, they still are the only way to create efficient hardware design implementations in FPGAs. It is true that we are moving towards software based design flows that will enable you to use FPGAs without having to know HDLs, or even basic hardware design principles but we are definitely not there yet. A good knowledge of either one of the two main HDL languages will be a useful skill for some years to come, especially if you consider yourself or want to become a hardware designer.

     

    The goal of this blog is two fold, trying to make it easier for beginners to climb the HDL mountain and for experienced designers to increase the level of abstraction and productivity when writing HDL code. This will take time at the current rate of one post per week, I am trying to add a new post every Tuesday so please have patience. I read all the comments and they will help me drive the posts in the right direction so please keep them coming.

  • Oh goody, Language Wars!

     

    We've had some interesting discussions of the years here in the FPGA Group about Verilog and VHDL.  Here are a couple of 2014 discussions I found this morning:

     

    Alternatives to VHDL/Verilog for hardware design

     

    Connecting Verilog to Synthesis

     

    I'm going to repeat part of a comment I made in the first discussion:

    I don't like Verilog or VHDL.  Given the choice, I mostly use Verilog since I don't want to type more than necessary and I have limited storage space for listings.

     

    My main problem with Verilog and VHDL is that they were designed for simulation.  Synthesis was added as an afterthought.  It's quite difficult for an inexperienced user to know how to write Verilog to get the synthesizer (I mostly use Xilinx's XST) to create the logic the user wants.  XST matches "language templates" to find things like flip-flops, registers, and RAMs.  "Language templates" are hidden in ISE's Edit menu.  Many new users don't know about the templates, and merrily write Verilog or VHDL from textbooks and it simulates fine.  Then they try to synthesize and get frustrated.

     

    Here's how I write Verilog: I imagine what hardware I want, and then I write my Verilog to match the template for each piece of hardware.  This is basically compiling in reverse: you imagine the object code, and then write your source code so that the compiler does the right thing.  I'm probably better at this than most designers since I've written compilers and digital design tools, so it's easy for me to guess at what Xilinx tools do.

    The second discussion is a typical example of what happens when a new user takes Verilog that simulates correctly and tries to synthesize.

     

    Of the commercial HDLs I've used over the years, my favorite is AHDL (Altera's HDL).  It let me describe the hardware I wanted more easily and I didn't have to jump through hoops to cajole the synthesizer into doing what I wanted.

  • Yes, I remember the wars well.

    The die hard hardware folks were very biased about any "software" like description language for implementing the sacred hardware circuits.

     

    To be fair, their were equal battles among the various software languages and passions ran very high.

     

    As a systems engineer, I readily saw the value of circuit description languages, and as the lines of software and hardware blurred, I found it very useful that everyone was using similar constructs to describe what the entire system was intended to do. The similarities allowed both sides to easily agree to where the logic transitioned between subsystems.

     

    DAB