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The Art of FPGA Design

fpgaguru

Hi,

 

This is a new blog on the Art of FPGA Design. For those who want to follow along, I will try to add a new post every week. You may want to check recent 2021 posts at the end about improved VHDL-2008 support in Vivado 2021.2.

 

While intended mainly for beginners initially, this is not an FPGA 101 kind of material. There are many of them that can be found online, including some excellent ones here on the Element 14 site. Some familiarity with FPGAs, HDLs and hardware design in general will be assumed. Some software programming experience might help (or hinder, we will have to see) but is not really necessary.

 

I will talk mainly about Xilinx FPGAs and VHDL in my posts but this blog is not intended to promote a particular FPGA manufacturer or HDL or design flow so no flaming please. The subjects I will talk about will be general enough to apply to other FPGAs, different HDLs or even other hardware design flows. I am not here to promote Xilinx FPGAs or products but this is my main area of expertise and this is what I will be talking about.

 

I will be targeting two different groups of users. On one hand I will address engineering students, hobbyists or even young engineers who have some basic knowledge of hardware design, would be interested in learning how to use FPGAs but are dissuaded by the financial entry costs and the very steep learning curve. My main goal is to provide some pointers and show that the path is not as expensive and difficult as it seems at first.

 

At the same time, I will also try to talk about some really advanced design matters, related to using VHDL and especially VHDL-2008 to do high performance FPGA design, which should be of interest even to very seasoned hardware designers.

 

In my first few posts I will try to give you a taste of both directions and then based on the feedback I will hopefully receive, I will steer the blog in the direction that interests most readers or even split it into two separate beginner and advanced tracks.

 

Full disclosure:

 

While I do work for Xilinx, this is my personal blog. The ideas expressed here are my own and do not represent the views or opinions of my employer. Although I will talk about Xilinx FPGAs among other things, this is not a hidden marketing promotional campaign - this is a technical blog about the Art of FPGA Design.

 

The code examples that will be used here are placed in the public domain and can be freely used by anybody without any restrictions, although providing attribution would be nice. On the other hand they come with no warranty of any kind, they are provided "as is" and you use them at your own risk.

 

So, without any further ado, let's go to the first blog post, which will try to dispel the perception that the entry into the field of FPGA design is financially difficult and for that reason an almost insurmountable barrier for most beginners.

 

The Art of FPGA Design - Post 1 - Running Out of Excuses

The Art of FPGA Design - Post 2 - Why learn FPGA Design?

The Art of FPGA Design - Post 3 - Two Free VHDL Books

The Art of FPGA Design - Post 4 - What's Your Type?

The Art of FPGA Design - Post 5 - Beyond STD_LOGIC

The Art of FPGA Design - Post 6 - VHDL User Defined Types

The Art of FPGA Design - Post 7 - We're Not in Kansas Anymore

The Art of FPGA Design - Post 8 - The Universal DELAY Building Block

The Art of FPGA Design - Post 9 - The Universal DELAY Building Block Part 2, the one with the cake

The Art of FPGA Design - Post 10  - Instantiating LUT6 Primitives

The Art of FPGA Design - Post 11 - Instantiating LUT6 Primitives Part 2

The Art of FPGA Design - Post 12 - The Universal MUX Building Block

The Art of FPGA Design - Post 13 - The Universal MUX Building Block Part 2

The Art of FPGA Design - Post 14 - The Universal MUX Building Block Part 3, the one with the Dutch Cocoa Box and the Ouroboros

The Art of FPGA Design - Post 15 - Counters, Adders and Accumulators

The Art of FPGA Design - Post 16 - The Carry-Save Adder, two for the price of one

The Art of FPGA Design - Post 17 - Using the Carry-Save Adder, Computing a Running Average

The Art of FPGA Design - Post 18 - Using the Carry-Save Adder, A Generic Adder Tree

The Art of FPGA Design - Post 19 - Using the Carry-Save Adder, The Constant Coefficient Multiplier

The Art of FPGA Design - Post 20 - The DSP48 Primitive

The Art of FPGA Design - Post 21 - The DSP48 Primitive - Behavioral FIR Inference

The Art of FPGA Design - Post 22 - The DSP48 Primitive - Behavioral Symmetric FIR Inference

The Art of FPGA Design - Post 23 - The DSP48 Primitive - Instantiating the DSP48

The Art of FPGA Design - Post 24 - The DSP48 Primitive - FIR with DSP48 Primitive Instantiations

The Art of FPGA Design - Post 25 - The DSP48 Primitive - Symmetric FIR with DSP48 Primitive Instantiations

The Art of FPGA Design - Post 26 - The DSP48 Primitive - Wide XOR Mode

The Art of FPGA Design - Post 27 - The DSP48 Primitive - Small Multiplications - Two For the Price of One

The Art of FPGA Design - Post 28 - The DSP48 Primitive - Inferring larger multipliers

The Art of FPGA Design - Post 29 - The DSP48 Primitive - Complex Multipliers

The Art of FPGA Design - Post 30 - The DSP58 Primitive

The Art of FPGA Design - Post 31 - Sorting and Searching Algorithms

The Art of FPGA Design - Post 32 - Sorting Networks

The Art of FPGA Design - Post 33 - Sorting Networks - The Batcher or odd-even mergesort sorting algorithm

The Art of FPGA Design - Post 34 - Sorting Networks - The VHDL implementation of Batcher's sorting algorithm

The Art of FPGA Design - Post 35 - Sorting Networks - The results for the VHDL implementation of Batcher's sorting algorithm

The Art of FPGA Design - Post 36 - Sorting Networks - The Verification Problem

 

New 2021 posts

The Art of FPGA Design - Post 37 - Vivado VHDL-2008 Support

 

New 2023 posts

The Art of FPGA Design - Post 38 - VHDL-2008 FP32 Support in Vivado

The Art of FPGA Design - Post 39 - The New DSPFP32 Primitive in Versal FPGAs

The Art of FPGA Design - Post 40 - Instantiating the DSPFP32 the Easy Way

If you found this blog interesting, you may want to follow

 

The Art of FPGA Design Season 2 - Digital Signal Processing, from Algorithm to FPGA Bitstream 

  • in reply to fpgaguru

    <email redacted after use>

     

    I sometimes use GitHub GIST to post code for blogs. It just requires pasting the code, and you get a URL you can share or put in the articles.

  • in reply to Jan Cumps
      function "*"(X,Y:SFIXED) return SFIXED is

     

        variable SX:SIGNED(X'high-X'low downto 0);

        variable SY:SIGNED(Y'high-Y'low downto 0);

        variable SR:SIGNED(SX'high+SY'high+1 downto 0);

        variable R:SFIXED(X'high+Y'high+1 downto X'low+Y'low);

      begin

        for K in SX'range loop

          SX(K):=X(X'low+K);

        end loop;

        for K in SY'range loop

          SY(K):=Y(Y'low+K);

        end loop;

        SR:=SX*SY; -- SIGNED multiplication

        for K in SR'range loop

          R(R'low+K):=SR(K);

        end loop;

        return R;

      end;

     

      function "*"(X:SFIXED;Y:STD_LOGIC) return SFIXED is

      begin

        if Y='1' then

          return X;

        else

          return TO_SFIXED(0.0,X);

        end if;

      end;

     

    I have a version of types_pkg.vhd with many helpful functions, but I do not see a way to attach files to these comment replies. If you give me your e-mail address I can send that to you directly. 

  • The blog series builds a library called types_pkg.

    I've been checking all blogs to collect the functions that uses throughout: https://gist.github.com/jancumps/622591b9a9a74c24e081a8b7407d7a1a

     

    I have:

      function TO_SFIXED(R:REAL;H,L:INTEGER) return SFIXED;
  function TO_SFIXED(R:REAL;HL:SFIXED) return SFIXED;
  function RESIZE(X:SFIXED;H,L:INTEGER) return SFIXED;
  function RESIZE(X:SFIXED;HL:SFIXED) return SFIXED;
  function MIN(A,B:INTEGER) return INTEGER;
  function MIN(A,B,C:INTEGER) return INTEGER;
  function MIN(A,B,C,D:INTEGER) return INTEGER;
  function MED(A,B,C:INTEGER) return INTEGER;
  function MAX(A,B:INTEGER) return INTEGER;
  function MAX(A,B,C:INTEGER) return INTEGER;
  function MAX(A,B,C,D:INTEGER) return INTEGER;
  function "+"(X,Y:SFIXED) return SFIXED;
  function "*"(X,Y:SFIXED) return SFIXED;

     

    I am missing:

      function "*"(X,Y:SFIXED) return SFIXED;

     

    If you find the missing one, or more that are expected to be in the lib, please ping, and I can update the GIST.

  • in reply to fpgaguru

    Hi Catalin,

     

    thanks for your answer, I am glad to hear that. Wish you all the best for your recovery and I am already looking forward to reading more.

     

    Simon

  • in reply to stickbreaker

    Hi,

     

    Thanks for your kind words, I am glad you found the blog useful. The blog is not discontinued, I just took a longer break due to personal reasons (eye surgery) but I plan to resume weekly postings very soon.

     

    Catalin