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Blog The Art of FPGA Design - Post 3
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  • Author Author: fpgaguru
  • Date Created: 24 Jul 2018 3:53 PM Date Created
  • Views 2179 views
  • Likes 10 likes
  • Comments 5 comments
  • vhdl
  • fpga_art
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The Art of FPGA Design - Post 3

fpgaguru
fpgaguru
24 Jul 2018

Two Free VHDL Books

 

If you installed Vivado WebPACK, the free version of Xilinx FPGA design tools, you are ready now to start creating your first hardware design. There are at least three different ways to program a Xilinx FPGA today, using a hardware description language like VHDL or Verilog/SystemVerilog, using Vivado HLS using C/C++ and Vivado SystemGenerator or ModelComposer which requires Matlab and Simulink. Each design flow has advantages and disadvantages and the third one is not free.

 

HDL languages like VHDL and Verilog are mature design languages, FPGA design in the last 20 years has been done more or less entirely using HDL flows. HLS is a much more recent design flow, it provides a higher abstraction level and faster simulation times but lower performance in terms of speed and device utilization.

 

We will start for now by using VHDL. In the 90s we had a fierce HDL language war, hardware designers debating endlessly which one is better, VHDL or Verilog? It turned out that both sides were right and the best tool is the one you know how to use. Today's HDL simulation and synthesis tools let you mix and match the two HDL languages and you can use other people's code in your design even if it is not your favorite HDL dialect.

 

This will not be a VHDL 101 style course, I will assume that you have at least a basic level knowledge of the language. If that's not the case, in the same spirit of free everything I highly recommend Peter Ashenden's 1990 "The VDHL Cookbook" - old but good, it's the book I used to learn VHDL:

https://tams.informatik.uni-hamburg.de/vhdl/doc/cookbook/VHDL-Cookbook.pdf

 

Another good resource is "Free Range VHDL, the no-frills guide to writing powerful code for your digital implementations" by Fabrizio Tappero, Bryan Mealy. You can download a free PDF copy from here:

http://freerangefactory.org/

 

Finally, not a free book but a very useful one if you want to bring your VHDL coding skills into the 21st century "VHDL 2008: Just the New Stuff" by the same Peter Ashenden and Jim Lewis, a well known VHDL expert:

https://www.amazon.com/VHDL-2008-Stuff-Systems-Silicon/dp/0123742498/ref=sr_1_1?ie=UTF8&qid=1531850195&sr=8-1&keywords=VHDL-2008+just+the+new

 

In the next few posts I will talk about VHDL coding styles and how to create efficient and high speed FPGA designs, how to write generic and reusable code, VHDL-93 vs VHDL-2008 and other similar subject matters.

 

Back to the top: The Art of FPGA Design

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Top Comments

  • fpgaguru
    fpgaguru over 7 years ago in reply to johnbeetem +4
    Yes, the HDL language wars are a thing of the past, we have moved along. If you live in Verilog land you should probably start looking into SystemVerilog. If you are trying to learn Verilog right now you…
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  • gustavovelascoh
    gustavovelascoh over 4 years ago

    Hi Catalin, thanks for your series of posts on FPGA. I will give FPGA a try (again). On this post you mentioned that HLS design flow is good in terms of abstraction, simulation time and time to market, but poor in performance. Is this still the case today (2 years after)? Thanks

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  • gustavovelascoh
    gustavovelascoh over 4 years ago

    Hi Catalin, thanks for your series of posts on FPGA. I will give FPGA a try (again). On this post you mentioned that HLS design flow is good in terms of abstraction, simulation time and time to market, but poor in performance. Is this still the case today (2 years after)? Thanks

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  • fpgaguru
    fpgaguru over 4 years ago in reply to gustavovelascoh

    Hi Gustavo, nothing has changed much and I do not expect a major change in the near future either. There is a place for every design language and flow, each one has its strengths and weaknesses. The ideal would be to be able to seamlessly mix HLS and HDL blocks in the same design, we are moving in that direction but it will take time.

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