A rudimentary 1st stab at the state machine for the BH1790 VHDL block:

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;

ENTITY bh1790 IS
  GENERIC(
    input_clk : INTEGER := 50_000_000;   --input clock speed from user logic in Hz
    sampling_count   : INTEGER := 32;    --sampling count - samples are grouped by this count (one I implement it)
    sampling_frequency : integer := 32); -- sampling frequency in Hz
  PORT(
    clk       : IN     STD_LOGIC;                    --system clock
    reset_n   : IN     STD_LOGIC;                    --active low reset
    -- data interface
    data_out  : OUT    std_logic_vector(31 downto 0);-- 32 bit raw sensor data 
                                                     -- [1][0][3][2] - [0x5500][0x5400][0x5700][0x5600]
                                                     -- [ledoff data][ledon data]
    debug_register : out std_logic_vector(7 downto 0); -- to remove. 8 pins to validate internal statuses, clocks, ...
    -- connections to i2c driver
    ena       : OUT    STD_LOGIC;                    --latch in command
    addr      : OUT    STD_LOGIC_VECTOR(6 DOWNTO 0); --address of target slave
    rw        : OUT    STD_LOGIC;                    --'0' is write, '1' is read
    data_wr   : OUT    STD_LOGIC_VECTOR(7 DOWNTO 0); --data to write to slave
    busy      : IN     STD_LOGIC;                    --indicates transaction in progress
    data_rd   : IN     STD_LOGIC_VECTOR(7 DOWNTO 0); --data read from slave
    ack_error : IN     STD_LOGIC);                   --flag if improper acknowledge from slave
END bh1790;

ARCHITECTURE bh1790 OF bh1790 IS
  CONSTANT divider  :  INTEGER := (input_clk/sampling_frequency); 
  TYPE machine_state IS (reset,init,active); --needed states
  signal s_debug_register : std_logic_vector (7 downto 0) := (others => '0');
  signal state : machine_state;
  
procedure i2c_commands (
 init : in STD_LOGIC) is -- if init, the reset command will be added. In that case, mandatory wait 1/32 second
begin
  -- todo: write the i2c registers.
  if (init = '1') then   -- only reset during initialisation.
    -- reset register
  end if; 
  -- register 1, 2, 3, refresh always as advised by datasheet
end i2c_commands; 
  
BEGIN

  PROCESS(clk, reset_n)
    VARIABLE sample_clock_count  :  INTEGER RANGE 0 TO divider;  --timing for clock generation
    VARIABLE samples_count : integer range 0 to sampling_count;
    
  BEGIN
    IF(reset_n = '0') THEN                --reset asserted
      state <= reset;
      sample_clock_count := 0;
      samples_count := 0;
      s_debug_register(7 downto 0) <= (others => '0'); -- debug: reset status
    ELSIF(rising_edge(clk)) THEN
        s_debug_register(0) <= '1'; -- todo remove debug: reset status
        sample_clock_count := sample_clock_count + 1;               --continue clock generation timing
        if (sample_clock_count = divider) then -- do every sample frequency tick
          s_debug_register(1) <= not s_debug_register(1); -- todo remove debug: toggle each time
          case  state is
            when reset =>
              i2c_commands('1');
            when others =>
              -- there should be no default handling
          end case;
          sample_clock_count := 0;
          samples_count := samples_count + 1;
          if (samples_count = sampling_count) then -- do every sampling_count sample tick
            s_debug_register(2) <= '1'; -- todo remove 
            samples_count := 0;            
          else -- do every sample tick except on the sampling_count'st sample
            s_debug_register(2) <= '0'; -- todo remove       
          end if;
        end if;
    END IF;
  END PROCESS;  

  debug_register (7 downto 0) <= s_debug_register (7 downto 0);
  
  END bh1790;

Not functional at all, but you can start to sense how the object flow will work.
Some VHDL constructs used:

• overridable generic for clock frequency, desired sample frequency and desired sample count for grouping, filtering and calculation
• a procedure, with 1 input parameter
• state machine with CASE and a custom TYPE for the states

Time to start working on real i2c communication. The hardware is set up:

The heart rate monitor is connected to the 2 i2c pins defined in the constraints. PMODA 1 (scl) and 2 (sda):

I've hooked up a protocol analyser. This should show me if traffic is valid.

Time to start working on real i2c communication. The hardware is set up:

The heart rate monitor is connected to the 2 i2c pins defined in the constraints. PMODA 1 (scl) and 2 (sda):

I've hooked up a protocol analyser. This should show me if traffic is valid.

Baby steps again. I see that there is intent to communicate.
The capture is not what I expected, but at least I know that the right pins are addressed.