You Can Participate in the "7 Ways to Leave Your Spartan-6" Program Even if You had Not Received a Free Board

Well, the 25th person decided to pass on participating. So, I'll have to look at my alternates and notify a new applicant.

No, We are waiting to hear back. We don't send anything out EVEr if one does not respond to my notification letter. If they don't at all, I choose another person.

You are correct about the download times of the VITIS tools using ADSL, I also have a slow ADSL connection and I have suffered.
I applied because during this year I had participated in another Xilinx competition and I already had the tools installed and had tested them.
In the previous competition I panicked with the development tools, I remember taking 2 months to have everything ready after trying multiple versions and operating systems. That is why in the tutorials I indicate which environment I am using.
With the tools installed it has been a surprise how well everything works and I only see new things to learn.

Using the FPGA group is somewhat confusing, I understand that there are FPGA professionals using it and these blogs may add unnecessary noise. It is everyone's responsibility to create quality content that is useful to the entire interested community.

25 boards? The challengers page lists 24 people. Have you left some unfortunate person off the list?

Whilst it's good to extend the opportunity to participate to others, you do have a solid list of contenders (I recognise a lot of the user names as having made good contributions to the community), so I think this one should go well.

I considered applying but was put off when I started investigating what I would need to run Vivado. On my basic ADSL line it would be a 9 hour download and then wouldn't run anyway because I'm using an old i3 laptop with Win 8.1. As a contrast, Lattice Diamond and Intel Quartus were both small downloads and run quite happily on my old OS, and I've just installed iCEcube2 and that seems fine too (though I haven't done a full project with it yet). I'm not complaining - Xilinx don't need to cater for people like me - but it does mean the competition would rapidly turn into a 'fiddling around with computers' exercise (a VM and something free based on RHEL, maybe?) and I'd rather just be doing things with FPGAs and CPLDs. So I'm a spectator for this one. Hopefully some of the entrants will show me how to do interesting DSP stuff, though anything using the PL is interesting.

Why did you decide to use the FPGA group rather than a dedicated challenge group? Was that driven by the sponsor or did the impetus for that come from e14 (it's a change from what you've previously done)?

Thank you Randall!
I've had the board for two weeks now and I encourage anyone who wants to get started with FPGAs to get involved.
Xilinx has done an incredible job together with Digilent so that you can start without having much idea of hardware as it is in my case. I have prepared two blogs following the Digilent reference tutorials and everything has been satisfying to see things working.

• Arty S7 50 First Power Up and Hardware-Only Blinky
• Arty S7 50 First Baremetal Software Project

I had a problem with the card, a voltage regulator was burned on the first day but the FPGA works perfectly and several members of the community have helped me so that I can skip that regulator if I need it.