Does the toolset for this FPGA is free? Is there link/url to the available ip core of kit?
I think I have managed to visualize the difference in behavior in the example. I am totally neophyte with verilog and with digital electronics. These are my first modules on Verilog. My hello world, but I think I am already understanding something.
`timescale 1ns/100ps module blocking_assignment( input iA, iB, iX, output reg oC, oY); assign #2 oC = iA & iB; assign #2 oY = oC & iX; endmodule module non_blocking_assignment( input iA, iB, iX, CLK, output reg oC, oY); always @ (posedge CLK) begin #2 oC <= iA & iB; #2 oY <= oC & iX; end endmodule
Looking at the LEDs does not show the difference, which is part of the point of the demonstration. It is that exact same circuit, but the blocking statement evaluates the first AND gate before the second one, while the non-blocking statement is evaluating both AND gates at the same time so long at the clock is running. Understanding this different in the circuit that is otherwise the exact same is the key takeaway.
Verilog is just what they happened to be teaching in the digital logic classes at my university when I first was learning HDL. I've picked up VHDL in the field out of necessity when I have to take over a project that's already done in VHDL. But just because Verilog is what I learned first, that's just what I tend towards.
I understand the difference between blocking or non-blocking assignment. What I don't understand is what the example is trying to explain. What difference should I expect between the two modes in the example?
I have built the example with an Arduino MKR Vidor 4000
wire wY_b; wire wY_nb; wire wC_b; wire wC_nb; assign bMKR_D = wC_b; assign bMKR_D = wY_b; assign bMKR_D = wC_nb; assign bMKR_D = wY_nb; assign iX = bMKR_D; assign iA = bMKR_D; assign iB = bMKR_D; // Blocking statements assign wC_b = iA & iB; assign wY_b= wC_b & iX; // Non blocking statements always @(posedge wOSC_CLK) begin wC_nb <= iA & iB; wY_nb <= wC_nb & iX; end
A=1 B =1 X=1
A=1 B=1 X=0
A=1 B=0 X=1
Edited: added logic trace
I can't find what difference to expect between the two assignment modes for this particular example just by looking at the leds..
From the diagrams the blocking one is combinational logic and the non blocking one is sequential logic.
In any case, a big thanks, very interesting, I look forward to the next video.
Enjoyed the video. Look forward to more.
I learned VHDL in 1992 in college, one of the first versions of VHDL. It was a very intense course designing our own chip. Then I started working as an application programmer and I have practically forgotten everything. Now I try to learn Verilog just out of curiosity and fun.
"...Back then, we called the two statements you described as combinatorial and sequential..."
I could potentially see mixing such terminology being confusing for those coming from a discrete logic background.
Combinatorial/combinational logic in the discrete logic world would perhaps generally refer to logic where the output state would be dependent upon the input state at any given time.
Whereas sequential logic would perhaps generally refer to logic where the output state could depend not only on the current input state but also on the previous state, at the next clock cycle.
So far the comparison holds out.
However, in the video; at first glance, the logic diagram for blocking statements would perhaps appear to look more like combinatorial logic, whereas the logic diagram for non-blocking would perhaps appear to look more like sequential logic due to the addition of the clocks.
Depending upon which way 'your brain is wired', then this logic perhaps may now appear to be inverted from discrete logic terminology.
Great video Whitney !
I have not written HDL in a very long time ...
Back then, we called the two statements you described as combinatorial and sequential synchronous.
Referring to your video:
- non-blocking statement => combinatorial
- blocking statement => sequential synchronous
I agree that knowing the difference between the two is very important.
Interestingly, back then, the language I coded with depended on my location:
- when I worked on the west coast, I coded in Verilog
- when I worked on the east coast, I coded in VHDL
This may have must been coincidence, but was wondering if anyone else noticed this.
Since I joined Avnet, I have been coding in both Verilog and VHDL.
Again, have not touched these languages for quite a while now ... is anyone still using HDL languages ?