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2-Minute FPGAs: Blocking vs Nonblocking Statements in Verilog

Summer of FPGA
Blocking vs Nonblocking Statements in Verilog

FPGA Group | The Summer of FPGAs - Agenda

 

 

Join Whitney Knitter of Knitronics for two minutes as we discuss the logic and computer science behind programming with Lattice's ICE40 tinyFPGA! Today we discuss blocking vs nonblocking statements in Verilog! This's the first part in a series of videos and blog posts over the course of the Summer of FPGA.

 

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Additional Parts:

 

Product Name
iCE40 FPGAiCE40 FPGA
tinyFPGAtinyFPGA

 

Summer of FPGA 2-Minute FPGAs - More Videos Coming Soon!

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  • Great video Whitney !

    I have not written HDL in a very long time ...

    Back then, we called the two statements you described as combinatorial and sequential synchronous.
    Referring to your video:
    - non-blocking statement => combinatorial
    - blocking statement => sequential synchronous

    I agree that knowing the difference between the two is very important.

     

    Interestingly, back then, the language I coded with depended on my location:
    - when I worked on the west coast, I coded in Verilog

    - when I worked on the east coast, I coded in VHDL

    This may have must been coincidence, but was wondering if anyone else noticed this.

     

    Since I joined Avnet, I have been coding in both Verilog and VHDL.

    Again, have not touched these languages for quite a while now ... is anyone still using HDL languages ?

     

    Regards,

     

    Mario.

  • in reply to albertabeef

    Verilog is just what they happened to be teaching in the digital logic classes at my university when I first was learning HDL. I've picked up VHDL in the field out of necessity when I have to take over a project that's already done in VHDL. But just because Verilog is what I learned first, that's just what I tend towards.

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