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Documents Programmable Electronic Load - Analyse the Summing Node Zero Point
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  • Author Author: Jan Cumps
  • Date Created: 1 Dec 2017 4:08 PM Date Created
  • Last Updated Last Updated: 15 May 2020 3:38 PM
  • Views 8708 views
  • Likes 8 likes
  • Comments 107 comments
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Programmable Electronic Load - Analyse the Summing Node Zero Point

This blog documents investigates the feedback node of the electronic load that Robert Peter Oakes, jc2048 and Jan Cumps are designing.

It's an important spot in the load's design. It measures the set point and the feedback from the output.

When the output is driven to 0, it should be on a potential as close as possible to 0 V.

On the first prototype it's -0.2 V. Not so much off, but the negative value  influences our ADC measurements.

This document checks how we can get this node to 0 V.

image

 

Because this document is evolving, some comments below may be out of sync with the content. That's because the content is adapted based on the conversation.

The measurements taken here are based on the original design, without R32 in place and U3B + tied to ground.

The current sense side of R7 is connected to ground, and a variable negative voltage from 0 V down is applied to the current sense side of R8 to simulate current being sensed.

 

The circuit isn't complex. The set point is driven by a DAC. It's set to 0 for this test.

The second input to this node is OpAmp 3C. It has both inputs tied to ground so should theoretically have 0 V at the output.

On my board I measure a potential of -0.212V at the left side of R33.

I hope to get this closer to 0 V to ease the ADC a bit - its performance degrades with negative voltage at its inputs.

Like the other blogs for the electronic load, this is a working document that will be updated with findings from anyone who wants to chime in.

 

Behaviour at 0V

 

buzy image

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Top Comments

  • jc2048
    jc2048 over 7 years ago in reply to Robert Peter Oakes +4
    As you say, changing the op-amp is one possibility. There are bipolar op-amps with much lower bias currents, but an alternative nowadays is a precision CMOS op-amp (you'd have to check whether other characteristics…
  • Robert Peter Oakes
    Robert Peter Oakes over 7 years ago +3
    To hopefully simplify things a little We have this, Upper op amp is simply to provide an inversion of the measured value back tot he ADC, hence the gain of -1 Lower right op amp measures the volts across…
  • jc2048
    jc2048 over 7 years ago in reply to Jan Cumps +3
    Love the advertisement for "John's excellent probes". It's like one those things from the old days of American TV where the presenter would suddenly turn, look very earnestly at the camera, and start reading…
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  • Jan Cumps
    Jan Cumps over 6 years ago

    Latest measurements, with a 5V DC input:

     

    The DAC outputs 0.980 mV offset. From value 0 to 100, it does not move an inch.

    This is measured with the DAC not loaded, the output pin is floating (Behaviour in-circuit is the same).

     

    The DAC is fairly linear from 100 on. Abruptly it forms a sharp knee when the linear ramp rises above the offset (DAC measurements on the right part of the image below).

    To confuse you image the first point in the graph is the current when the DAC is set to 110, last when set to 100.

    For the voltage on the right, it's the other way around. This is the list with DAC set from 100 to 110.

    This is to keep you alert.

    image

     

    The load pulls 0.519 mA (you don't see that precision in the graph on the left, but I consulted the data behind it) when the DAC output is 0.980 MV

    From then on it rises fairly linear.

     

    When I short the DAC output, the current drops to 0.0016 µA, virtually the same as when I disable the load (0.0010 µA).

    It may turn out that the offset of the offset of the DAC is the cause for that low range knee after all....

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  • Jan Cumps
    Jan Cumps over 6 years ago in reply to Jan Cumps

    I've prototyped a "programmable" offset compensation circuit. A differentiator with an OpAmp (I used an UA741 because it's the only DIP I have lying around).

     

    image

    We have 3 spare DACs in our design. I'm using the second DAC to pull the offset of DAC1 to 0 V.

    This will also work if DAC2 has a higher offset as DAC 1. You just have to drive DAC1 to an equal or slightly higher value than DAC2's offset and call that 0.

    You'll loose that part of DAC1's range.

     

    I have Set DAC1 to 230. That's a point where it is performing good. Then I set DAC2 to 15 to set the output of the OpAmp to 0 V.

    Each step of DAC1 from then on nicely increments the OpAmps output.

     

    image

     

    edit: I could use the free ADC4 to measure and fix that offset automatically, so that it's not a thing that you have to do when building the load?

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  • Jan Cumps
    Jan Cumps over 6 years ago in reply to Jan Cumps

    ... I should of course measure before R5 ...

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  • jc2048
    jc2048 over 6 years ago in reply to Jan Cumps

    This is very good on why it can make a difference

     

    http://e2e.ti.com/blogs_/archives/b/thesignal/archive/2013/04/23/bypass-capacitors-yes-but-why

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  • Jan Cumps
    Jan Cumps over 6 years ago in reply to Jan Cumps

    Jan Cumps  wrote:

     

    No success yet.

    I am able to drive the output after R5 to 0 by playing with DAC 1 and 2, in esssence taking away the offset.

    But any little voltage I go over that voltage fully drives the FET, as if it pushes the integrator off balance.

    I 'll have to re-check connections, double check if I used the right resistor value for R5, measure the whole circuit probably.

    The fact that I've been working and changing components on the PCB often doesn't help with reliability either...

    I removed the compensation circuit and all works as before again.

     

    image

     

    On one side that's good news - I don't have to troubleshoot the original PCB.

    But something is wrong with my compensation circuit.

     

    image

     

    R2 gets the original DAC 1 outout,

    R1 uses DAC2 output to compensate the offset at 0

    R5 is connected to the summing node.

    In the original design, the opamp was not there and DAC 1 was connected to the summind point directly via a 100K resistor:

    image

     

    At least that is simple enough circuit to troubleshoot fairly easy ... It worked with a 471 on a breadboard ...

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  • Jan Cumps
    Jan Cumps over 6 years ago in reply to Jan Cumps

    jc2048, do I make a dummy mistake here with the impedances?

    When I use the output voltage of a DAC, through a 100K resistor, the eload reacts linear(ish).

     

    When I use that output through a *1 opamp, with a voltage on the - input for zero compenation.

    The output of that opamp is a, through a 100 K resistor, to the same point as  in the original design.

    As soon as the output of the opamp, measured before the 100K resistor (same point as where I measured the DAC voltage) reaches 0, the load goes to full drive.

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  • jc2048
    jc2048 over 6 years ago in reply to Jan Cumps

    I can't see anything obvious.

     

    The output of the op amp is a low impedance (much lower than the 100k). The op amp output open-loop isn't more than 100R at low frequencies and the feedback should bring it much, much lower. If you see a static voltage at the output it shouldn't be any different to what you see with the DAC providing that voltage. Is it static? What does a 'scope show?

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  • Jan Cumps
    Jan Cumps over 6 years ago in reply to jc2048

    I found it: all resistors on my bodge board are 100 Ohm instead of 100K. They overshout the 100K feedback on the summing node.

     

    my envelope witk 100K resistors contained 100 Ohm resistors.

    image

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  • Jan Cumps
    Jan Cumps over 6 years ago in reply to Jan Cumps

    undo

     

    image

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  • jc2048
    jc2048 over 6 years ago in reply to Jan Cumps

    I found it: all resistors on my bodge board are 100 Ohm instead of 100K.

    So they are. It was staring us in the face in that photograph you posted - '101' marked on the tops.

     

    Personally, I'd change them all for 10k (including the two summing resistors) to get the currents up an order of magnitude, but that's probably just me being fussy.

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  • Jan Cumps
    Jan Cumps over 6 years ago in reply to jc2048

    too late for now, everything is built up again. I can always do it at a later time.

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  • Jan Cumps
    Jan Cumps over 6 years ago in reply to jc2048

    It works now - with proper resistor values. I'll try to find a DAC1 DAC2 combination that gives a good start near 0..

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  • Jan Cumps
    Jan Cumps over 6 years ago in reply to jc2048

    It works now - with proper resistor values. I'll try to find a DAC1 DAC2 combination that gives a good start near 0..

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  • Jan Cumps
    Jan Cumps over 6 years ago in reply to Jan Cumps

    It still shows that jump when the circuit starts to load

    image

     

    edit: detail at the knee

     

    imageimage

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