Programmable Electronic Load - Analyse the Summing Node Zero Point

I'm going to redo this exercise now that the OpAmps are replaced with lower bias ones and I have more precise measurement tools.

From the blog Programmable Electronic Load - LabVIEW Test Automation: Characterise the Instrument we can see that the behaviour is very linear.

But we have a non-0 start point. When th DAC is driven to 0, there is an output current flowing of a few mA.

I assume that it's our control circuit that's doing that, because if I disable the output (pull the gate to ground), the current that flows is neglectable. And it's the same FET that's fully blocking the current flow then.

I've re-stacked the load so that the control board is on top and I have easier access to the measure point.

I can't use the LCD display in that case. I'll use the SCPI interface to set values.

I'll measure DAC output and the voltages at relevant control circuit points to see what drives the FET to conduct a little.

I think I'll document the results in new blog post. We can then think on measures to get the lowest current lower than 2 mA.

I've been checking for a while and get 0.6 µA when measuring with a multimeter. I usd a fairly high input voltage of 14 V to compensate for any cable resistance.

When I shortcut the DAC1 output, I get almost the same as when the output is off. So it seems that the offset is caused by offset of the DAC.

When driving the DAC to 0, I get 0.731 mV output. The measured voltage over the sensor resistor is then 0.054 mV.

If I shortcut DAC A, I measure 0.005 mV over the 0R05 sense resistor. That's virtually the same as INPUT OFF (0.003 mV).

I'll have to check if I can deal with the positive DAC offset ...

When I remove everything from the DAC, the offset voltage is 0.529 mV.

Same as when the eload is connected, the ADC DAC only starts to ramp up from that offset once the DAC value is close to 100.

I'll try to see what a 2K load at the output does to the voltage (tested with 10K and that does nothing - I don't have high hopes for 2K).

I'll also try to set the current with a potentiometer instead of the DAC, to see if I can control between 0 and 2mA then.

If I put a multi-turn pot between ground and VREF and feed that into the circuit, I should be able to rule out the whole analog circuit as cause for that difficulty to control the very low currents ...

Here's the test setup stack for that:

You can see that between the green PCB (the ADC/DAC board) and the purple one (control circuit), I've bent the pin for the DAC that controls the current setting of the load.

I'll replace that with the center tap of a potentiometer wired between 0 V and Vref.

Here are the measurements in the range below the offset of the DAC.

What's clear is that the analog control circuit can go much lower than what the DAC (in my setup) can control; because of its offset.

And the values are stable across a wide range of input voltages (I tested that while doing this exercise).

Good news for Robert Peter Oakes, because that indicates that his analog design is usable from 80 µA on. What we'll have to try now is close the gap between that 80µA and the >1 mA minimum when using the DAC as current setter.

edit: the lowest I can get with the DAC is a control voltage of 0.78. At that voltage, the current drawn by the load is 1.3 mA. The analog part can go as low as 0.08 mA. That's more than an order of magnitude lower. Worth pursuing, I think ...

Robert Peter Oakes, jc2048, I'm looking for the best place in the control circuit where we can inject a solution for DAC offset.

A good place here we can offset that DAC output when set to 0x0000.

If we can do that with injecting a positive voltage somewhere in the control circuit, we could use one of the free DAC channels to provide that compensaton, and use the calibration API to set that value.

It may not be that easy though. In my setup, DAC A has an offset of about 0.7 mV (Jon's DAC has less), and the DAC output doesn't change until the input value increases above that level.

But that's something we can work around in software. If we can compensate for the DAC offset voltage inserted into the integrator, I can adapt the firmware to start from that point on. We will lose about 100 values in total (out of 65000) as usable settings, but that's negligible.

... the discussion in Jon's build thread may give a solution for the impact of DAC A offset to the lowest range.

We can use a >> 100K resistor to insert some additional offset into the opamp 3C. Because it feeds back into the integrator, we can use that to undo the DAC A offset.

DAC B can be used to generate the offset.

On my board, the positive offset of approx 0.7 mA of DAC A causes that the load has a lowest range of > 1 mA.

Offsetting (sic) that offset via an additional signal into U3, makes that you can push the power fet down to its lowest conductance. The same value as when you switch off the input via Q1.

This has impact on the reported current by U3B, and I haven't analysed that yet. I hope I can correct that in firmware.

To get this additional circuitry added on the board isn't too hard. Get a 10M (I tested with 3M3 because because) 1206 resistor and place it on footprint C11.

Then put a bodge wire from the bottom side of C12 to pin 4 of connecor P3 (to tap off DAC B).

I've used the LabVIEW process to gather the current between DAC settings 0 and 300 to measure the current

I haven't analysed it yet.

The bump when the DAC kicks in has moved up but the bump is still abrupt and the lowest controlled current is still 2 mA ...

I'll use a more precise meter to measure the current. Unfortunately I can't log the results ...

Pushing the offset higher doesn't solve the issue. It just pushes it uphill.

In this graph, I set DAC B, that creates the offset correction, to 300.

Behaviour is the same, a steep jump from nothing to > 2 mA, but at a higher starting point of DAC A.

(are we fighting against the diodes at the backside of the integrator?)

Pushing the offset higher doesn't solve the issue. It just pushes it uphill.

In this graph, I set DAC B, that creates the offset correction, to 300.

Behaviour is the same, a steep jump from nothing to > 2 mA, but at a higher starting point of DAC A.

(are we fighting against the diodes at the backside of the integrator?)

My suggestion wasn't a good one. U3C is a differential amplifier configuration, so the input pins aren't always sitting close to ground (the pin you are injecting into isn't a 'virtual ground'). Since they move around, the current you inject will vary (in this case your DAC and resistor are a very poor approximation to a current source). I should have thought more about it before throwing the idea at you.

I'm currently working on the output board. Tomorrow I'll be in a position to wire the whole thing together and see how this one behaves.

I've tried option 1, adding a negative offset to the summing node.

Unbuffered. I made a voltage divider with a 10 K potentiometer between GND and -5, turned it to -2 mV and used a 100K resistor to feed it to the summing node.

Because it's unbuffered, the voltage moves closer to GND when the DAC1 is pushing current in the node.

No magic on the lowest level.

Can you measure the voltage at P7.1 so we can see what the integrator thinks it is telling the MOSFET to do as you go past the cut-off in the current.

Might be an idea to give it a look-over with a scope too. The meters might not be showing you the whole picture.

I'm adapting the test set to allow 4 additional measures using an oscilloscope. I'll start with P7.1

I don't have a LabVIEW capable DMM, so I'm using the scope as voltage probe.

I'm making it an optional instrument. I'd like to be able to run quick tests without having to set up the oscilloscope just to make it work.

Are you interested in the gate voltage with or without offset compensation? I'm running it without first (I've removed the compensation botches)?

Might be an idea to give it a look-over with a scope too. The meters might not be showing you the whole picture.

Todo

I have this working. I'm logging pin P7.A via the scope ...

jc2048  wrote:

 

Can you measure the voltage at P7.1 so we can see what the integrator thinks it is telling the MOSFET to do as you go past the cut-off in the current.

 

...

No offset remediation, 5 V input:

Current:

Gate voltage:

I've done the same measurement a second time. Even though the current graph is stable, the gate graph shows significant difference:

I'm doing the gate measurements again. I've just learned how to program the Bandwidth filter of my scope.

Well, it didn't smoothen that out

The input voltage this time was 6 volt.

Here is the same exercise with Scope bandwidth on and input voltage = 5 V.

The MOSFET behaviour is very interesting and I'd like to investigate that. I don't know much about how these power MOSFETs behave if you try and use them in the linear region like this - the manufacturer intends them as power switches, so the datasheet doesn't help very much - but if I had to guess, I'd say that maybe you're seeing the effect of having an array of MOSFETs in parallel, all with slightly different characteristics, and characteristics that change with temperature and so are dependent on how the currents arrange themselves (a power MOSFET like this will be an array of smaller MOSFETs). It's possible that down around the threshold voltage there's a certain amount of somewhat chaotic behaviour to the gate voltage (ie there might be several arrangements that allow for the small total current and which you get may depend on very subtle variations as you approach - if that were the case, it ought to be possible to repeat the measurement many times and map the various 'paths' through that area).

Anyway, that's just wild speculation [quite out of character for me!] and might be totally wrong - where are all the experts when you need them? It doesn't matter to you because the loop seems to be dealing with it quite happily.

Back to the load. I've just sat thinking about all this and it seems to me that you're asking a lot of this circuit. The sense resistor is 50mOhms, so for 1mA current you get 50uV on the sense. You then give it to an op amp with an offset voltage of 180uV (typ)/ 600uV(max) to deal with. I suspect we're getting to the point where you would need to think about trimming the offset on that first amplifier.

But do you actually need the load to be able to do this? Do you need the load to operate continuously over more than 4 decades of current? If you don't, perhaps you might do better to build two instruments covering different ranges.