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Documents Programmable Electronic Load - Analyse the Summing Node Zero Point
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  • Author Author: Jan Cumps
  • Date Created: 1 Dec 2017 4:08 PM Date Created
  • Last Updated Last Updated: 15 May 2020 3:38 PM
  • Views 10265 views
  • Likes 8 likes
  • Comments 107 comments
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Programmable Electronic Load - Analyse the Summing Node Zero Point

This blog documents investigates the feedback node of the electronic load that Robert Peter Oakes, jc2048 and Jan Cumps are designing.

It's an important spot in the load's design. It measures the set point and the feedback from the output.

When the output is driven to 0, it should be on a potential as close as possible to 0 V.

On the first prototype it's -0.2 V. Not so much off, but the negative value  influences our ADC measurements.

This document checks how we can get this node to 0 V.

image

 

Because this document is evolving, some comments below may be out of sync with the content. That's because the content is adapted based on the conversation.

The measurements taken here are based on the original design, without R32 in place and U3B + tied to ground.

The current sense side of R7 is connected to ground, and a variable negative voltage from 0 V down is applied to the current sense side of R8 to simulate current being sensed.

 

The circuit isn't complex. The set point is driven by a DAC. It's set to 0 for this test.

The second input to this node is OpAmp 3C. It has both inputs tied to ground so should theoretically have 0 V at the output.

On my board I measure a potential of -0.212V at the left side of R33.

I hope to get this closer to 0 V to ease the ADC a bit - its performance degrades with negative voltage at its inputs.

Like the other blogs for the electronic load, this is a working document that will be updated with findings from anyone who wants to chime in.

 

Behaviour at 0V

 

buzy image

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Top Comments

  • jc2048
    jc2048 over 8 years ago in reply to Robert Peter Oakes +4
    As you say, changing the op-amp is one possibility. There are bipolar op-amps with much lower bias currents, but an alternative nowadays is a precision CMOS op-amp (you'd have to check whether other characteristics…
  • Robert Peter Oakes
    Robert Peter Oakes over 8 years ago +3
    To hopefully simplify things a little We have this, Upper op amp is simply to provide an inversion of the measured value back tot he ADC, hence the gain of -1 Lower right op amp measures the volts across…
  • jc2048
    jc2048 over 8 years ago in reply to Jan Cumps +3
    Love the advertisement for "John's excellent probes". It's like one those things from the old days of American TV where the presenter would suddenly turn, look very earnestly at the camera, and start reading…
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  • Jan Cumps
    Jan Cumps over 8 years ago

    Some measurements (without any bodging, using the original schema.

     

    I simulated the voltage over the sense resistor with a power supply. The input voltage is measured close to opamp 3C inputs - any setup resistance is compensated for.

    In theory,

    • UC3 out should be input * 7.8
    • U3B out should be that value * -1
    • ADC B should be the same (and is image ) as U3B out

     

     

    *-7,8*-1opamp 3Copamp 3BADC BADC BADC Btheory ampsinputU3C outU3B outvoltrawabs000,109-0,213-0,213188-1136643990,4-0,02-0,05-0,051-0,0515625-276652470,8-0,04-0,210,1040,1051875455701,2-0,06-0,3580,2520,245438139213991,6-0,08-0,5210,4180,414937221622162-0,1-0,6780,5710,57131230463044

     

    The ADC is behaving good. it closely reflects the actual voltage represented at its input.

    The two opamps, both using non-precision resistors to set the gain, need compensation.

     

    I've graphed it. For ease of understanding, I've inverted the negative Y values so that a trend can be seen.

    • The X axis is the theoretical current as measured by a 0R50 resistor.
    • The red line is the voltage over the sense resistor (simulated by a power supply, measured close to opamp 3C input), inverted
    • The green line is the output of opamp U3C inverted,  it should reflect the X axis * -7.8 gain. It has a negative offset.
    • The light purple line is the output of U3B. It's -3C multied by -1 (this one is off - it should be spot on - it has an offset).
    • The light blue line is the output of U3B sampled by the ADC. I consider that "good enough" for the moment. Very close
    • The dark purple line is what we should get at the ADC, if opamp and resistors were optimal.

    image

    Thoughts on compensation?

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  • Jan Cumps
    Jan Cumps over 8 years ago in reply to Jan Cumps

    ... it seems that each opamp introduces a 0.1 V offset. If that's the case, compensation should be doable. At least everything behaves linear image

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  • Jan Cumps
    Jan Cumps over 8 years ago in reply to Jan Cumps

    It gets very close if I compensate for the DC offset of the two opamps at 0 V input!

     

    theory U3B outcompensated ADC measure0-0,0001880,1560,16143750,3120,3181870,4680,4584380,6240,6279370,780,784312

     

    The blue line is uncompensated ADC

    The dark purple one the expected (theoretical) value at ADC

    The orange one the compensated ADC.

    image

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  • Jan Cumps
    Jan Cumps over 8 years ago in reply to Jan Cumps

    It gets very close if I compensate for the DC offset of the two opamps at 0 V input!

     

    theory U3B outcompensated ADC measure0-0,0001880,1560,16143750,3120,3181870,4680,4584380,6240,6279370,780,784312

     

    The blue line is uncompensated ADC

    The dark purple one the expected (theoretical) value at ADC

    The orange one the compensated ADC.

    image

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  • jc2048
    jc2048 over 8 years ago in reply to Jan Cumps

    It might be easier to see what it's doing if you plot the difference between the expected and the measured. The dip at 1.2V is a concern - the rest looks like a positive offset of four or five millivolts, but there it reverses for some reason.

     

    After this you're going to have to consider what you do with the bias currents of the integrator op-amp.

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  • Jan Cumps
    Jan Cumps over 8 years ago in reply to Jan Cumps

    Taking only the 0 V offset in account, this is what I get when running the instrument at 0 A and 2 A:

     

    0 A (Vsense == 0.000 V):

    image

     

    2 A (Vsense == 0.100V):

    image

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  • Jan Cumps
    Jan Cumps over 8 years ago in reply to jc2048

    jc2048  wrote:

     

    ... The dip at 1.2V is a concern ...

    I suspect that to be an operator error. I have to repeat all measures, in the same order, with properly probing, to be sure.

    I don't see an obvious reason why opamps behave different at that particular value. Chances are fair that it's me ...

    (or the ADC, because the measured values in the previous graph don't show the dip, only the ADC's volts value - I'm not satisfied yet with the stability of the ADC samples, they fluctuate somewhat per request...)

     

    I haven't looked at the integrator's behaviour yet.

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  • Jan Cumps
    Jan Cumps over 8 years ago in reply to jc2048

    jc2048  wrote:

     

    It might be easier to see what it's doing if you plot the difference between the expected and the measured.

    Here's the data, based on the same measures:

       

    theory U3B outcompensated ADC measuredelta theory compensated0-0,0001880,0001880,1560,1614375-0,00543750,3120,318187-0,0061870,4680,4584380,0095620,6240,627937-0,0039370,780,784312

    -0,004312

     

    image

    Tomorrow I'll try to redo ...

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  • Jan Cumps
    Jan Cumps over 8 years ago in reply to Jan Cumps

    I redid the measurements today:

     

     

    *-7,8*-1opamp 3Copamp 3BADC BADC BADC Btheory ampsinput- inputU3C out- U3C outU3B outvoltrawabstheory U3B outcompensated ADC measuredelta theory compensatedgain0000,11-0,11-0,214-0,21337511406439900,000625-0,000625#DEL/0!0,4-0,020,02-0,0510,051-0,053-0,0511875282652640,1560,1628125-0,00681258,1406250,8-0,040,04-0,2040,2040,0990,0993755325320,3120,313375-0,0013757,8343751,2-0,060,06-0,3630,3630,2580,258375137513750,4680,472375-0,0043757,872916666666671,6-0,080,08-0,5170,5170,4110,411219421940,6240,625-0,0017,81252-0,10,1-0,6720,6720,5650,566813302330230,780,780813-0,0008137,80813

     

    image

     

    Redoing the measurement after it has been on for a while for -0.02 V input brings it more in line:

     

    *-7,8*-1opamp 3Copamp 3BADC BADC BADC Btheory ampsinput- inputU3C out- U3C outU3B outvoltrawabstheory U3B outcompensated ADC measuredelta theory compensatedgain0,4-0,020,02-0,0470,047-0,056-0,05625303652340,1560,15775-0,001757,8875

     

    that results in this gain graph and this error between expected and measured value at ADC:

    image

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  • Jan Cumps
    Jan Cumps over 8 years ago in reply to Jan Cumps

    My power supply, scopes and this instrument support SCPI. Maybe I should automate this in LabVIEW ...

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  • Jan Cumps
    Jan Cumps over 8 years ago in reply to Jan Cumps

    It's been a while but I'm getting the hang of it again.

    image

     

    Upper part is the electronic load. The LabVIEW flow throws a *IDN command to it.

    The lower part is a RIGOL power supply. LabVIEW configures the first channel, then enables it and logs some data.

     

    Now I'll try to combine the two and read some ADC data back from the load ...

     

    The Rigol part is described here: Automate Rigol Power Supply with LabVIEW

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  • Jan Cumps
    Jan Cumps over 8 years ago in reply to Jan Cumps

    Progress:

    image

     

    I'm able to det the PSU to a particular setting, then read from the electronic load, then set the PSU to the next voltage.

    It must be possible to save such a block as a module but I'm not that advanced in LabVIEW yet.

    It does show that I can make this work though - have a PSU and the load talk together in an automated script.

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