Actions
Engagement
  • Author Author: Jan Cumps
  • Date Created: Date Created
  • Last Updated Last Updated:
  • Views 10262 views
  • Likes 8 likes
  • Comments 107 comments
Related
Recommended

Programmable Electronic Load - Analyse the Summing Node Zero Point

This blog documents investigates the feedback node of the electronic load that , and are designing.

It's an important spot in the load's design. It measures the set point and the feedback from the output.

When the output is driven to 0, it should be on a potential as close as possible to 0 V.

On the first prototype it's -0.2 V. Not so much off, but the negative value  influences our ADC measurements.

This document checks how we can get this node to 0 V.

image

 

Because this document is evolving, some comments below may be out of sync with the content. That's because the content is adapted based on the conversation.

The measurements taken here are based on the original design, without R32 in place and U3B + tied to ground.

The current sense side of R7 is connected to ground, and a variable negative voltage from 0 V down is applied to the current sense side of R8 to simulate current being sensed.

 

The circuit isn't complex. The set point is driven by a DAC. It's set to 0 for this test.

The second input to this node is OpAmp 3C. It has both inputs tied to ground so should theoretically have 0 V at the output.

On my board I measure a potential of -0.212V at the left side of R33.

I hope to get this closer to 0 V to ease the ADC a bit - its performance degrades with negative voltage at its inputs.

Like the other blogs for the electronic load, this is a working document that will be updated with findings from anyone who wants to chime in.

 

Behaviour at 0V

 

buzy image

Parents

  • Some measurements (without any bodging, using the original schema.

     

    I simulated the voltage over the sense resistor with a power supply. The input voltage is measured close to opamp 3C inputs - any setup resistance is compensated for.

    In theory,

    • UC3 out should be input * 7.8
    • U3B out should be that value * -1
    • ADC B should be the same (and is image ) as U3B out

     

     

    *-7,8*-1opamp 3Copamp 3BADC BADC BADC Btheory ampsinputU3C outU3B outvoltrawabs000,109-0,213-0,213188-1136643990,4-0,02-0,05-0,051-0,0515625-276652470,8-0,04-0,210,1040,1051875455701,2-0,06-0,3580,2520,245438139213991,6-0,08-0,5210,4180,414937221622162-0,1-0,6780,5710,57131230463044

     

    The ADC is behaving good. it closely reflects the actual voltage represented at its input.

    The two opamps, both using non-precision resistors to set the gain, need compensation.

     

    I've graphed it. For ease of understanding, I've inverted the negative Y values so that a trend can be seen.

    • The X axis is the theoretical current as measured by a 0R50 resistor.
    • The red line is the voltage over the sense resistor (simulated by a power supply, measured close to opamp 3C input), inverted
    • The green line is the output of opamp U3C inverted,  it should reflect the X axis * -7.8 gain. It has a negative offset.
    • The light purple line is the output of U3B. It's -3C multied by -1 (this one is off - it should be spot on - it has an offset).
    • The light blue line is the output of U3B sampled by the ADC. I consider that "good enough" for the moment. Very close
    • The dark purple line is what we should get at the ADC, if opamp and resistors were optimal.

    image

    Thoughts on compensation?

  • in reply to Jan Cumps

    ... it seems that each opamp introduces a 0.1 V offset. If that's the case, compensation should be doable. At least everything behaves linear image

  • in reply to Jan Cumps

    It gets very close if I compensate for the DC offset of the two opamps at 0 V input!

     

    theory U3B outcompensated ADC measure0-0,0001880,1560,16143750,3120,3181870,4680,4584380,6240,6279370,780,784312

     

    The blue line is uncompensated ADC

    The dark purple one the expected (theoretical) value at ADC

    The orange one the compensated ADC.

    image

  • in reply to Jan Cumps

    It might be easier to see what it's doing if you plot the difference between the expected and the measured. The dip at 1.2V is a concern - the rest looks like a positive offset of four or five millivolts, but there it reverses for some reason.

     

    After this you're going to have to consider what you do with the bias currents of the integrator op-amp.

  • in reply to Jan Cumps

    Taking only the 0 V offset in account, this is what I get when running the instrument at 0 A and 2 A:

     

    0 A (Vsense == 0.000 V):

    image

     

    2 A (Vsense == 0.100V):

    image

Comment Children
No Data