This is the Final Project Blog of International Design Challenge Path to Programmable III.
In the beginning, I intended a very complex project which after modification will be filed for Patent but this Ultra96V2G from 'Avnet Engineering Services' is MPSoC with 6 processors, need very complex coding and minimum handling of 2 softwares- Vivado and Vitis which can have add on with MATLAB,Altium, Orcad, PSPICE, COMSOL,Flowtherm, ANSYS etc. This is not simpler like Arduino(my Arduino board is dead), where 2 copied code lines or simple commands work.
And my sophisticated project need according to me is 2yrs approx( had been working since 2010 on my personal prototype). So, not showing it as in my blog 1 is no cause of guilty as I have successfully deeply explored Ultra96V2G with datsheets, study training material from Avnet, and reference manuals.
I started late working on project, thought the codes will easily run and some of the available files (which are given on internet with demo) will run smoothly but nothing worked, and I ought to depend on only myself. Due to this, this final blog I have completely re-written 3-5 times..
During the last days of submission, synthesis wasted time of a week, then jtag cable, vivado/vitis re-installation and yesterday again computer crash. I m thankful to Mr. Randall for accepting 1 day delay in the submission of project (its around 7hrs 15 min delay) and also to e14 staff for promptly releasing blogs from bot. Rest journey and feedback of this program is in the last section of this page.
In this blog/Final Project, I will demonstrate the use of AES-Ultra96V2-G, on Thermal Management, Finite Element Analysis (FEA), Computational Fluid Dynamics (CFD), Cryptography, UltraScale+ Irrigation and designing of Custom IPs. The UltraScale+ Irrigation is incomplete but time is up and some work on pumps from PWM could be shown. I have to mention it as it was my submitted proposal.
Following tasks are demonstrated on Ultra96V2G : -
- Demo 1,ila_design_1 : TCL Build Up
- DEMO : ILA_pwm version 1 - Custom IP (Not in Repository) : 24 PWM (Pulse Width Modulation) controllers- Pump 1, Pump 2, Relay 1, Relay 2, 16 Transistors and 3 additional PWM , in daisy chain.
- DEMO : ILA_pwm version 2 - Custom IP (Not in Repository) : 8 PWM (Pulse Width Modulation) controllers, in daisy chain.
- DEMO : ILA_adc - Custom IP (Not in Repository) : A 12-bit SAR ADC (Analog to Digital Converter)
- DEMO : ILA_sha256 - Custom IP (Not in Repository) : Cryptography Secure Hash Algorithm - 256
- DEMO : Thermal Management, Finite Element Analysis & Computational Fluid Dynamics
- Failed Demonstrations
- DEMO : Zynq Ultrascale+ I2C, GPIO, Sleep,Reset and U-Boot
- DEMO : LCD MiniClick
- DEMO : 2 LEDs controlled by PWM/Interrupts Click Mezzanine
- DEMO : Pump, 2 Soil Moisture Sensors
Note : Custom IP are made by me ( not verified by AMD experts). I have uploaded complete designed IPs. It is elementary for any diploma or engineer or phd engineer. For other demonstrations, only snippets.
As can be seen, I m not demonstrating a single project but multi-disciplines, so the explanation of a particular demonstration is mentioned in its section only.
Table of Contents
- External Items(Not From Kit)
- Pump 1 and Pump 2 with its base & connector
- Some Components
- 5 Soil Moisture Sensors
- 60 pin High Speed Header
- Water Pipes
- Relay 1 and Relay 2
- Ubuntu/Linux USB AMD Drivers
- Click Mezzanine Mechanical STEP files
- Mechanical STEP Files
- DXF File
- Schematic
- Pin-Outs
- 96Boards Click Mezzanine 40-pin expansion
- 96Boards Click Mezzanine UART
- 96Boards Click Mezzanine I2C
- 96Boards Click Mezzanine Power and Reset
- 96Boards Click Mezzanine SPI
- 96Boards Click Mezzanine PCM/I2S
- 96Boards Click Mezzanine GPIO
- Click Mezzanine
- LCD LMB162XFW
- Click Mezzanine RST pin Test
- Click Mezzanine 1 & 2, Two mikroBUS sockets Voltage Testing
- Click Mezzanine 40-pin expansion Voltage Testing
- Demo 1,ila_design_1 :TCL Build Up of Zynq Ultrascale+, 7 different MMCM clocks, 7 reset processor systems, interrupt controller, BRAM and Block Memory Generator
- Demo 2 : Custom IP, ILA_pwm version 1 - 24 PWM Controllers
- Demo 3 : Custom IP, ILA_pwm version 2 - 8 PWM Controllers
- Demo 4 : Custom IP, ILA_adc - 12-bit SAR ADC
- Demo 5 : Custom IP, ILA_sha256 - Cryptography Secure Hash Algorithm -256
- Custom IP, ILA_aes_encrypt & ILA_aes_decrypt - Cryptography Advanced Encryption Standard
- ILA_aes_encrypt
- ILA_aes_decrypt
- Custom IP : ILA_CortexR4
- Demo 6 : Thermal Management, Finite Element Analysis & Computational Fluid Dynamics
- Failed Demonstrations
- Mobile Wifi, Bluetooth & Android Applet
- Keypad, Click Mezzanine and LCD Mini Click
- Keypad, Click Mezzanine and LCD (older type)
- LMS6DSL
- Demo 7 : Zynq Ultrascale+ I2C, GPIO, Sleep, Reset and U-Boot
- Demo 8 : LCD MiniClick
- Demo 9 : 2 LEDs controlled by PWM/Interrupts Click Mezzanine
- Pump, 2 Soil Moisture Sensors
- Suggestions to Update DataSheet and Training
- Path Programmable 3 Journey & Summary
- Synthesis
- Training
- Suggestion For Future
1. External Items (Not From Kit)
1) Pump 1 and Pump 2 with its base & connector
Water Pump Specification
- Input Voltage : 24 VDC
- Nominal Flow Rate : 1.8 LPM
- Max. Pump output : 150 psi
- Max. inlet pressure : 60 psi
- Winding : Full Copper
2) Some Components
Resistances, Capacitors, Varistor, BJT, diodes, MOSFETs, MOS driver, Spring, Inductor, Potentiometer, buzzer, LCD 16x2, 4 x 4 Matrix keypad module, TMP36, ADXL335, connecting wires and breadboard
3) 5 Soil Moisture Sensors
4) 60 pin High Speed Header
After connecting this on Ultra96V2G
5) Water Pipes
6) Relay 1 and Relay 2
7) Ubuntu/Linux USB AMD Drivers
This is not an item to be listed in this section but many engineer graduates will need this. And whoever will read this blog can easily find.
To download drivers : Ubuntu/Linux USB AMD Drivers
So, firstly I show up setup, which was expected to work in some way and it did worked only partially, but some things fully; may be the scope is too big.
2. Click Mezzanine Mechanical STEP files
2.1 Filename : HW_Click Mezzanine_v103_Output Files_CAD_Click Mezzanine_v103_Step.zip
From Reference Designs, I have opened STEP files of Mechanical Drawings in CAD software and here are results
a) Front View
b) Left
c) Top
d) Back
e) Bottom
f) Isometric View 1
g) Isometric View 2
2.2 DXF File
Filename : HW_Click Mezzanine_v103_Output Files_CAD_Click Mezzanine_v103_DXF
3. Pin-Outs
Without the knowledge of the following pin outs, connections not possible.
3.1 96Boards Click Mezzanine 40-pin expansion
The low- speed 2 x 20 female 2mm header, 4.5mm height, 40-pin J5 of Ultra96 V2G is connected with 40-pin Click Mezzanine (96Boards).
3.2 96Boards Click Mezzanine UART
3.3 96Boards Click Mezzanine I2C
3.4 96Boards Click Mezzanine Power and Reset
3.5 96Boards Click Mezzanine SPI
3.6 96Boards Click Mezzanine PCM/I2S
3.7 96Boards Click Mezzanine GPIO
3.8 Click Mezzanine
3.9 LCD LMB162XFW
In this project , I have used both LCD's- the old one's 16 x 2 and the one provided LMB162XFW.
The given LCD is LMB162XFW, which is used with Click Mezzanine using LCD Mini Click. The display of this LCD is also 2 x 16 monochrome with 5 x 8 dot font. The input voltages are 3.3V or 5V. The pinout is as
3.10 Click Mezzanine RST pin Test
The video initially shows Ultra96V2-G has powered up by blue light. Then Click Mezzanine 96 Boards is put on and RST button is pressed.
Ultra96V2-G resets and redlight can be seen, it then resets and powers up again with blue light.
3.11 Click Mezzanine 1 & 2, Two mikroBUS sockets Voltage Testing
Click Mezzanine board comes with 1 and 2, Two mikroBUS sockets where each mikroBUS sockets has 3.3 V and 5 V.
Socket 1 : The multimeter testing shows 3.31 voltage instead 3.3 V and 4.86 V instead 5 V.
Socket 2 : The multimeter testing shows 3.32 voltage instead 3.3 V and 4.87 V instead 5 V.
3.12 Click Mezzanine 40-pin expansion Voltage Testing
In the pin-outs of 40-pin expansion, In the pin-outs of 40-pin expansion,
Pin 37 has +5V, but multimeter shows + 4.87V
Pin 38 is SYS_DCIN and mulitmeter shows 11.72 V.
Pin 35 has +1V8, 1.8 V and mulitmeter reading it near this voltage.
3.13) 60 pin High Speed Header
I have mentioned this in 'External Items (Not From Kit)'
From these, pins 1,3,5,7,9,11,13,15,17 and 19 used.
4. Demo 1, ila_design_1 : TCL Build Up of Zynq Ultrascale+, 7 different MMCM clocks, 7 reset processor systems, interrupt controller, BRAM and Block Memory Generator
Using the scripting language TCL (Tool command language)
1) Project and simulator language is set to VHDL and bd design name 'ila_design_1' is created
set_property target_language VHDL [current_project]
set_property simulator_language VHDL [current_project]
create_bd_design "ila_design_1"
2) Then Zynq Ultrascale+ block properties are set
// Author: Abhishek Bansal
set_property -dict [list \
CONFIG.PSU_BANK_0_IO_STANDARD {LVCMOS18} \
CONFIG.PSU_BANK_1_IO_STANDARD {LVCMOS18} \
CONFIG.PSU_BANK_2_IO_STANDARD {LVCMOS18} \
CONFIG.PSU_BANK_3_IO_STANDARD {LVCMOS18} \
CONFIG.PSU__DDRC__BUS_WIDTH {32 Bit} \
CONFIG.PSU__DDRC__MEMORY_TYPE {LPDDR 4} \
CONFIG.PSU__USE__FABRIC__RST {0} \
CONFIG.PSU__USE__M_AXI_GP2 {0} \
CONFIG.PSU__FPGA_PL0_ENABLE {0} \
CONFIG.PSU__CSU__PERIPHERAL__ENABLE {1} \
CONFIG.PSU__DISPLAYPORT__PERIPHERAL__ENABLE {0} \
CONFIG.PSU__DPAUX__PERIPHERAL__IO {MIO 34 .. 37} \
CONFIG.PSU__DP__LANE_SEL {Dual Lower} \
CONFIG.PSU__GPIO0_MIO__PERIPHERAL__ENABLE {1} \
CONFIG.PSU__GPIO1_MIO__PERIPHERAL__ENABLE {1} \
CONFIG.PSU__GPIO2_MIO__PERIPHERAL__ENABLE {1} \
CONFIG.PSU__GPIO_EMIO__PERIPHERAL__ENABLE {1} \
CONFIG.PSU__I2C1__PERIPHERAL__ENABLE {1} \
CONFIG.PSU__I2C1__PERIPHERAL__IO {MIO 4 .. 5} \
CONFIG.PSU__PMU__EMIO_GPI__ENABLE {1} \
CONFIG.PSU__PMU__EMIO_GPO__ENABLE {1} \
CONFIG.PSU__PMU__PERIPHERAL__ENABLE {1} \
CONFIG.PSU__SD0__GRP_CD__ENABLE {1} \
CONFIG.PSU__SD0__PERIPHERAL__ENABLE {1} \
CONFIG.PSU__SD0__PERIPHERAL__IO {MIO 13 .. 16 21 22} \
CONFIG.PSU__SD0__SLOT_TYPE {SD 2.0} \
CONFIG.PSU__SD1__PERIPHERAL__ENABLE {1} \
CONFIG.PSU__SD1__PERIPHERAL__IO {MIO 46 .. 51} \
CONFIG.PSU__SD1__SLOT_TYPE {SD 2.0} \
CONFIG.PSU__SPI0__GRP_SS1__ENABLE {1} \
CONFIG.PSU__SPI0__PERIPHERAL__ENABLE {1} \
CONFIG.PSU__SPI0__PERIPHERAL__IO {MIO 38 .. 43} \
CONFIG.PSU__SPI1__PERIPHERAL__ENABLE {1} \
CONFIG.PSU__SWDT0__PERIPHERAL__ENABLE {1} \
CONFIG.PSU__SWDT1__PERIPHERAL__ENABLE {1} \
CONFIG.PSU__TTC0__PERIPHERAL__ENABLE {1} \
CONFIG.PSU__TTC1__PERIPHERAL__ENABLE {1} \
CONFIG.PSU__TTC2__PERIPHERAL__ENABLE {1} \
CONFIG.PSU__TTC3__PERIPHERAL__ENABLE {1} \
CONFIG.PSU__UART0__PERIPHERAL__ENABLE {1} \
CONFIG.PSU__UART0__PERIPHERAL__IO {MIO 2 .. 3} \
CONFIG.PSU__UART1__PERIPHERAL__ENABLE {1} \
CONFIG.PSU__USB0__PERIPHERAL__ENABLE {1} \
CONFIG.PSU__USB1__PERIPHERAL__ENABLE {1} \
CONFIG.PSU__USB3_0__PERIPHERAL__ENABLE {1} \
CONFIG.PSU__USB3_0__PERIPHERAL__IO {GT Lane2} \
CONFIG.PSU__USB3_1__PERIPHERAL__ENABLE {1} \
CONFIG.PSU__CRL_APB__CPU_R5_CTRL__DIVISOR0 {3} \
CONFIG.PSU__CRL_APB__PL0_REF_CTRL__DIVISOR0 {4} \
CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__DIVISOR0 {8} \
CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__DIVISOR0 {8} \
CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__DIVISOR0 {8} \
CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__DIVISOR0 {8} \
CONFIG.PSU__OVERRIDE__BASIC_CLOCK {1} \
CONFIG.PSU__USE__M_AXI_GP0 {1}\
] [get_bd_cells zynq_ultra_ps_e_0]
save_bd_design
validate_bd_design
3) In my training Blog3, I had used only 1 clock, but now here I will test R&D on 7 different clocks. Then 7 clocking circuits are created from 25 MHz to 600 MHz
// Author: Abhishek Bansal
clock
set_property -dict [list \
CONFIG.CLKOUT2_JITTER {102.086} \
CONFIG.CLKOUT2_PHASE_ERROR {87.180} \
CONFIG.CLKOUT2_REQUESTED_OUT_FREQ {200.000} \
CONFIG.CLKOUT2_USED {true} \
CONFIG.CLKOUT3_JITTER {94.862} \
CONFIG.CLKOUT3_PHASE_ERROR {87.180} \
CONFIG.CLKOUT3_REQUESTED_OUT_FREQ {300.000} \
CONFIG.CLKOUT3_USED {true} \
CONFIG.CLKOUT4_JITTER {90.074} \
CONFIG.CLKOUT4_PHASE_ERROR {87.180} \
CONFIG.CLKOUT4_REQUESTED_OUT_FREQ {400.000} \
CONFIG.CLKOUT4_USED {true} \
CONFIG.CLKOUT5_JITTER {83.768} \
CONFIG.CLKOUT5_PHASE_ERROR {87.180} \
CONFIG.CLKOUT5_REQUESTED_OUT_FREQ {500.000} \
CONFIG.CLKOUT5_USED {true} \
CONFIG.MMCM_CLKOUT1_DIVIDE {6} \
CONFIG.MMCM_CLKOUT2_DIVIDE {4} \
CONFIG.MMCM_CLKOUT3_DIVIDE {3} \
CONFIG.MMCM_CLKOUT4_DIVIDE {2} \
CONFIG.NUM_OUT_CLKS {5} \
CONFIG.CLKOUT5_REQUESTED_OUT_FREQ {600.000} \
CONFIG.CLKOUT6_JITTER {132.683} \
CONFIG.CLKOUT6_PHASE_ERROR {87.180} \
CONFIG.CLKOUT6_REQUESTED_OUT_FREQ {50.000} \
CONFIG.CLKOUT6_USED {true} \
CONFIG.CLKOUT7_JITTER {154.057} \
CONFIG.CLKOUT7_PHASE_ERROR {87.180} \
CONFIG.CLKOUT7_REQUESTED_OUT_FREQ {25.000} \
CONFIG.CLKOUT7_USED {true} \
CONFIG.CLK_OUT1_PORT {clk_100} \
CONFIG.CLK_OUT2_PORT {clk_200} \
CONFIG.CLK_OUT3_PORT {clk_300} \
CONFIG.CLK_OUT4_PORT {clk_400} \
CONFIG.CLK_OUT5_PORT {clk_600} \
CONFIG.CLK_OUT6_PORT {clk_50} \
CONFIG.CLK_OUT7_PORT {clk_25} \
CONFIG.MMCM_CLKOUT5_DIVIDE {24} \
CONFIG.MMCM_CLKOUT6_DIVIDE {48} \
CONFIG.NUM_OUT_CLKS {7} \
CONFIG.CLKOUT3_REQUESTED_OUT_FREQ {300.01896} \
CONFIG.CLKOUT4_REQUESTED_OUT_FREQ {400.02528} \
CONFIG.CLKOUT5_REQUESTED_OUT_FREQ {600.03792} \
CONFIG.CLKOUT6_REQUESTED_OUT_FREQ {50.00316} \
CONFIG.CLKOUT7_REQUESTED_OUT_FREQ {25.00158} \
CONFIG.CLKOUT2_REQUESTED_OUT_FREQ {200.01264}\
CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {100.00632}\
] [get_bd_cells clk_wiz_0]
The primitive chosen is MMCM(Mixed-Mode Clock Manager) instead pure PLL. Below are the clocking primitive attributes used
- Multi Counter = 49.375
- Clock 1 Period = 3.429
- Clock 2 period = 10.0
- Reference Jitter = 0.010
4) Then 7 reset processor systems for the above 7 clocking circuits are created from 25 MHz to 600 MHz
// Author: Abhishek Bansal
set_property name proc_sys_reset_100m [get_bd_cells proc_sys_reset_0]
set_property name proc_sys_reset_300m [get_bd_cells proc_sys_reset_102]
set_property name proc_sys_reset_200m [get_bd_cells proc_sys_reset_101]
set_property name proc_sys_reset_400m [get_bd_cells proc_sys_reset_103]
set_property name proc_sys_reset_600m [get_bd_cells proc_sys_reset_104]
set_property name proc_sys_reset_50m [get_bd_cells proc_sys_reset_105]
set_property name proc_sys_reset_25m [get_bd_cells proc_sys_reset_106]
5) Then interrupt controller is set up which concentrates multiple interrupt inputs from peripheral devices to a single interrupt output and connects one or more AXI memory-mapped master devices to one or more AXI memory mapped slave devices
// Author: Abhishek Bansal
set_property -dict [list \
PFM.IRQ {intr {id 0 range 32}} \
CONFIG.C_EN_CASCADE_MODE {0} \
][get_bd_cells axi_intc_0]
6) PL Block RAM, JTAG to AXI Master and Block Memory Generator added as in Blog 3. The validation of TCL till now is shown below :
7) The resource estimation report is
8) The clock summary is
9) Package block is
10) The clock interaction report is destination clocks vs source clocks
11) Power report is
12) Schematic is
13) Simulation report is
// Author: Abhishek Bansal
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
parameter GRES_WIDTH = 10000;
parameter GRES_START = 10000;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
wire GRESTORE;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
reg GRESTORE_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (strong1, weak0) GSR = GSR_int;
assign (strong1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
assign (strong1, weak0) GRESTORE = GRESTORE_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
initial begin
GRESTORE_int = 1'b0;
#(GRES_START);
GRESTORE_int = 1'b1;
#(GRES_WIDTH);
GRESTORE_int = 1'b0;
end
endmodule
`endif
14) The utilization report is
---------------------------------------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2023.1 (lin64) Build 3865809
| Author : Abhishek Bansal
| Design : ila_design_1_wrapper
| Device : xczu3eg-sbva484-1-e
| Speed File : -1
| Design State : Synthesized
---------------------------------------------------------------------------------------------------------------------------------------------
Utilization Design Information
Table of Contents
-----------------
1. CLB Logic
1.1 Summary of Registers by Type
2. BLOCKRAM
3. ARITHMETIC
4. I/O
5. CLOCK
6. ADVANCED
7. CONFIGURATION
8. Primitives
9. Black Boxes
10. Instantiated Netlists
1. CLB Logic
------------
+----------------------------+-------+-------+------------+-----------+-------+
| Site Type | Used | Fixed | Prohibited | Available | Util% |
+----------------------------+-------+-------+------------+-----------+-------+
| CLB LUTs* | 7663 | 0 | 0 | 70560 | 10.86 |
| LUT as Logic | 6093 | 0 | 0 | 70560 | 8.64 |
| LUT as Memory | 1570 | 0 | 0 | 28800 | 5.45 |
| LUT as Distributed RAM | 1132 | 0 | | | |
| LUT as Shift Register | 438 | 0 | | | |
| CLB Registers | 10537 | 0 | 0 | 141120 | 7.47 |
| Register as Flip Flop | 10537 | 0 | 0 | 141120 | 7.47 |
| Register as Latch | 0 | 0 | 0 | 141120 | 0.00 |
| CARRY8 | 2 | 0 | 0 | 8820 | 0.02 |
| F7 Muxes | 7 | 0 | 0 | 35280 | 0.02 |
| F8 Muxes | 0 | 0 | 0 | 17640 | 0.00 |
| F9 Muxes | 0 | 0 | 0 | 8820 | 0.00 |
+----------------------------+-------+-------+------------+-----------+-------+
1.1 Summary of Registers by Type
--------------------------------
+-------+--------------+-------------+--------------+
| Total | Clock Enable | Synchronous | Asynchronous |
+-------+--------------+-------------+--------------+
| 0 | _ | - | - |
| 0 | _ | - | Set |
| 0 | _ | - | Reset |
| 0 | _ | Set | - |
| 0 | _ | Reset | - |
| 0 | Yes | - | - |
| 0 | Yes | - | Set |
| 111 | Yes | - | Reset |
| 322 | Yes | Set | - |
| 10104 | Yes | Reset | - |
+-------+--------------+-------------+--------------+
2. BLOCKRAM
-----------
+-------------------+------+-------+------------+-----------+-------+
| Site Type | Used | Fixed | Prohibited | Available | Util% |
+-------------------+------+-------+------------+-----------+-------+
| Block RAM Tile | 6.5 | 0 | 0 | 216 | 3.01 |
| RAMB36/FIFO* | 6 | 0 | 0 | 216 | 2.78 |
| RAMB36E2 only | 6 | | | | |
| RAMB18 | 1 | 0 | 0 | 432 | 0.23 |
| RAMB18E2 only | 1 | | | | |
+-------------------+------+-------+------------+-----------+-------+
* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E2 or one FIFO18E2. However, if a FIFO18E2 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E2
3. ARITHMETIC
-------------
+-----------+------+-------+------------+-----------+-------+
| Site Type | Used | Fixed | Prohibited | Available | Util% |
+-----------+------+-------+------------+-----------+-------+
| DSPs | 0 | 0 | 0 | 360 | 0.00 |
+-----------+------+-------+------------+-----------+-------+
4. I/O
------
+------------+------+-------+------------+-----------+-------+
| Site Type | Used | Fixed | Prohibited | Available | Util% |
+------------+------+-------+------------+-----------+-------+
| Bonded IOB | 1 | 0 | 0 | 82 | 1.22 |
+------------+------+-------+------------+-----------+-------+
5. CLOCK
--------
+----------------------+------+-------+------------+-----------+-------+
| Site Type | Used | Fixed | Prohibited | Available | Util% |
+----------------------+------+-------+------------+-----------+-------+
| GLOBAL CLOCK BUFFERs | 7 | 0 | 0 | 196 | 3.57 |
| BUFGCE | 7 | 0 | 0 | 88 | 7.95 |
| BUFGCE_DIV | 0 | 0 | 0 | 12 | 0.00 |
| BUFG_PS | 0 | 0 | 0 | 72 | 0.00 |
| BUFGCTRL* | 0 | 0 | 0 | 24 | 0.00 |
| PLL | 0 | 0 | 0 | 6 | 0.00 |
| MMCM | 1 | 0 | 0 | %2 0 3 | 33.33 |
+----------------------+------+-------+------------+-----------+-------+
* Note: Each used BUFGCTRL counts as two GLOBAL CLOCK BUFFERs. This table does not include global clocking resources, only buffer cell usage. See the Clock Utilization Report (report_clock_utilization) for detailed accounting of global clocking resource availability.
6. ADVANCED
-----------
+-----------+------+-------+------------+-----------+--------+
| Site Type | Used | Fixed | Prohibited | Available | Util% |
+-----------+------+-------+------------+-----------+--------+
| PS8 | 1 | 0 | 0 | 1 | 100.00 |
| SYSMONE4 | 0 | 0 | 0 | 1 | 0.00 |
+-----------+------+-------+------------+-----------+--------+
7. CONFIGURATION
----------------
+-------------+------+-------+------------+-----------+-------+
| Site Type | Used | Fixed | Prohibited | Available | Util% |
+-------------+------+-------+------------+-----------+-------+
| BSCANE2 | 0 | 0 | 0 | 4 | 0.00 |
| DNA_PORTE2 | 0 | 0 | 0 | 1 | 0.00 |
| EFUSE_USR | 0 | 0 | 0 | 1 | 0.00 |
| FRAME_ECCE4 | 0 | 0 | 0 | 1 | 0.00 |
| ICAPE3 | 0 | 0 | 0 | 2 | 0.00 |
| MASTER_JTAG | 0 | 0 | 0 | 1 | 0.00 |
| STARTUPE3 | 0 | 0 | 0 | 1 | 0.00 |
+-------------+------+-------+------------+-----------+-------+
8. Primitives
-------------
+------------+-------+---------------------+
| Ref Name | Used | Functional Category |
+------------+-------+---------------------+
| FDRE | 10104 | Register |
| LUT3 | 2718 | CLB |
| LUT6 | 1883 | CLB |
| RAMD32 | 1698 | CLB |
| LUT5 | 1121 | CLB |
| LUT4 | 1100 | CLB |
| LUT1 | 685 | CLB |
| LUT2 | 590 | CLB |
| FDSE | 322 | Register |
| SRL16E | 245 | CLB |
| RAMS32 | 242 | CLB |
| SRLC32E | 193 | CLB |
| RAMD64E | 160 | CLB |
| FDCE | 111 | Register |
| MUXF7 | 7 | CLB |
| BUFGCE | 7 | Clock |
| RAMB36E2 | 6 | BLOCKRAM |
| CARRY8 | 2 | CLB |
| RAMB18E2 | 1 | BLOCKRAM |
| PS8 | 1 | Advanced |
| MMCME4_ADV | 1 | Clock |
| INBUF | 1 | I/O |
| IBUFCTRL | 1 | Others |
+------------+-------+---------------------+
9. Black Boxes
--------------
+------------+------+
| Ref Name | Used |
+------------+------+
| dbg_hub_CV | 1 |
+------------+------+
10. Instantiated Netlists
-------------------------
+-------------------------------------+------+
| Ref Name | Used |
+-------------------------------------+------+
| ila_design_1_zynq_ultra_ps_e_0_0 | 1 |
| ila_design_1_smartconnect_0_0 | 1 |
| ila_design_1_rst_ps8_0_291M_8 | 1 |
| ila_design_1_proc_sys_reset_100_5 | 1 |
| ila_design_1_proc_sys_reset_100_4 | 1 |
| ila_design_1_proc_sys_reset_100_3 | 1 |
| ila_design_1_proc_sys_reset_100_2 | 1 |
| ila_design_1_proc_sys_reset_100_1 | 1 |
| ila_design_1_proc_sys_reset_100_0 | 1 |
| ila_design_1_proc_sys_reset_0_0 | 1 |
| ila_design_1_jtag_axi_0_0 | 1 |
| ila_design_1_clk_wiz_0_0 | 1 |
| ila_design_1_axi_intc_0_4 | 1 |
| ila_design_1_axi_bram_ctrl_0_bram_0 | 1 |
| ila_design_1_axi_bram_ctrl_0_0 | 1 |
| ila_design_1_auto_pc_0 | 1 |
+-------------------------------------+------+
5. Demo 2 : Custom IP, ILA_pwm Version 1
Version 1 : ILA_pwm - 24 PWM Controllers
I made Custom IP (Not in Repository) for PWM (Pulse Width Modulation), 24 PWM controllers. To distinguish from my created repository, I have named it as 'ILA_pwm'
- Pump 1
- Pump 2
- Relay 1
- Relay 2
- 16 Transistors (will be used in DC- DC converter and inverter in future work, not in this project)
- 3 additional PWM (will be used in DC- DC converter and inverter in future work, not in this project)
1) The device generated by this custom IP, ILA_pwm
2) The timing report of ILA_pwm
3) The I/O Bank details, duty cycle, PWM counter of custom IP, ILA_pwm
4) The power report of custom IP, ILA_pwm
5) The schematic of custom IP, ILA_pwm
6) Adding this Custom IP, ILA_pwm to My project, with dutycycle and pwmcounter counters visible
7) Adding this Custom IP, ILA_pwm to My project, and wiring
8) Basic Validation check of this Custom IP, ILA_pwm to My project, Successful
9) The resource estimation report of his step, (new resource estimation report will be generated after some modifications)
6. Demo 3 : Custom IP, ILA_pwm Version 2
Version 2 : ILA_pwmv2
Description : Eight Independent PWM Controllers with 8 time periods, 8 duty cycles, 8 counters, 8 Interrupts in Daisy Chain
This version 2 is improved version in coding, and I have myself deprecated Version 1 as version1 has same time period across all 24 PWM controllers and 1 interrupt line. In this version2, 8 different time periods can be entered and 8 interrupts are given for independent control.
Note : Custom IP, ILA_pwmv2 is made by me ( not verified by AMD experts). It is elementary.
Pls read 'synthesis Feedback' in the last section of this page. So, the IP demo is shown in simulation, vivado simulator, and its synthesis and with this IP only. Complete project all together passes validation check, gives no error, generates HDL wrapper but hangs on synthesis.
In my ILA_pwmv2,
- c0,c1,c2,c3,c4,c5,c6,c7,c8 are 8 counters
- d0,d1,d2,d3,d4,d5,d6,d7,d8 are 8 duty cycles
- pwm0,pwm1,pwm2,pwm3,pwm4,pwm5,pwm6,pwm7,pwm8 are 8
1) Complete custom IP which gives the following results can be downloaded here : ILA_pwmv2
2) Timing Summary Report, pls download here : Custom IP : ILA_pwmv2 - Timing Summary Report
3) Video has complete tour with even integration with main project, System Management Wizard, ILA and validation check. Thats why, I named it as ILA_pwmv2
7. Demo 4 : Custom IP, ILA_adc - 12-bit SAR ADC
Description : I2C/SPI Compatible 12-bit SAR ADC
I made Custom IP (Not in Repository). To distinguish from my created repository, I have named it as 'ILA_adc'. These will be used to interface any of ADCs like 5 Soil moisture sensors, Voltage & current of 255W Solar Panel, TMP36. It will also tested with I2C and SPI inteface.
Note : Custom IP, ILA_adc is made by me ( not verified by AMD experts). It is elementary.
Pls read 'synthesis Feedback' in the last section of this page. So, the IP demo is shown in simulation, vivado simulator, and its synthesis and with this IP only. Complete project all together passes validation check, gives no error, generates HDL wrapper but hangs on synthesis.
In my ILA_adc,
- SCK is Serial Clock
- DO is Serial Data Out
- CS is Chip Select
- CH0 is analog input
1) Complete custom IP in VHDL which gives the following results can be downloaded here : ILA_adc
2) Video has complete tour with even integration with main project, System Management Wizard, ILA and validation check. Thats why, I named it as ILA_adc
8. Demo 5 : Custom IP, ILA_sha256 - Cryptography Secure Hash Algorithm - 256
Ultra96-V2-G supports Secure-hash algorithm (SHA) functions SHA-1, SHA-224, and SHA-256. The SHA-2 family consists of hash functions SHA-224, and SHA-256.
I made Custom IP (Not in Repository) for cryptography, SHA-256, which has digest or hash value with 256 bits.
Note : Custom IP, ILA_sha256 is made by me ( not verified by AMD experts). It is elementary.
Pls read 'synthesis Feedback' in the last section of this page.
1) Complete custom IP in VHDL can be downloaded from here : ILA_sha256
Known algorithm from MIT (Massachusetts Institute of Technology) is pasted. So, I got idea whether can I make IPs or not.
2) Pc freezes on synthesis after 7-8hrs running.
So, cannot make video has like above ones. 2 screenshots of Custom IP, ILA_sha256
9. Custom IP, ILA_aes_encrypt & ILA_aes_decrypt - Cryptography Advanced Encryption Standard
Pls note AES can be confusing for some, as with Ultra96V2-G, AES- Ultra96V2-G, AES mean Avnet Engineering Services. With Cryptography, AES mean Advanced Encryption Standard.
I made Custom IP (Not in Repository) for cryptography, Advanced Encryption Standard (AES).
AMD has 1 IP for AES but it is not free, it can be purchased from AMD.
I have separated encryption and decryption in 2 different IPs. To distinguish from my created repository, I have named it as 'ILA_aes_encrypt & ILA_aes_decrypt '. I have referred AMD documentation and tried to create replica of AMD's AES. AMD has only 1 IP where encryption or decryption has to be chosen.
ILA_aes_encrypt
In my ILA_aes_encrypt IP, the
- key128 is 128 bits
- key192 is 192 bits
- key256 is 256 bits
- key512 is 512 bits
- iv is Initialization Vector of 128 bits
- ecb128 is 128-bit Electronic Code Book
- ecb192 is 192-bit Electronic Code Book
- ecb256 is 256-bit Electronic Code Book
- cfb is 128-bit Cipher FeedBack
- GCM is 128-bit Galois Counter Mode
I gave this up, as computer will freeze as in the the previous section, I have got idea whether I can make such cryptography IPs or not.
This PC will again crash and today is 4th sept. Also, I will copy known algorithm of AES and paste only. So, giving up.
10. Custom IP, ILA_CortexR4
I made Custom IP (Not in Repository) for ARM Cortex R4.
AMD gives ARM Cortex-M1 and M3 IP for free but not Cortex-R4.
I have referred AMD documentation. To distinguish from my created repository, I have named it as 'ILA_CortexR4'. This I will use in future work to interface with TMS570LS04, automotive-grade microcontroller for safety systems, on its launchpad board TI Hercules LaunchPad. Hope, these boards (Ultra96V2-G or TMS570LS04) won't die unexpectedly like my one of the boards - unexpected death of Arduino MKR 1000 : see here 1 and here 2 .
Note : Custom IP, ILA_Cortex R4 is made by me ( not verified by AMD experts). Also, I do not intend ILA_Cortex R4 to work in the same way as Cortex M1 or Cortex M3, so it eliminates lot of coding. That is, I do not intend to design whole processor but something what I specifically need, I designed this. Whether achieved or not can be said after practical testing on two boards, for which currently I m running out of time.
In my ILA_CortexR4, there are 4 timers, 6 interrupts, 2 I2C, 2 SPI, Reset, Clock and 4 GPIOs
- Four Timers - N2HET0, N2HET1, N2HET2 and N2HET3 are 32-bit High-End Timers compatible with TMS570LS04
- IRQ0, IRQ1, IRQ2 and IRQ3 are Four 32-bits Interrupts
- IRQ640, IRQ641 are Two 64-bit Interrupts
- SDA0 and SDA1 is Serial Data0 and Serial Data1
- SCL0, SCL1, SCK0 & SCK1 are four Serial Clocks
- SDO0, SD01 is Serial Data Out for 1st and 2nd SPI
- SDI0, SDI1 is Serial Data In for 1st and 2nd SPI
- CS0, CS1 is Chip Select for 1st and 2nd SPI
- RST is reset
- CLK is clock
- GPIO0, GPIO1, GPIO2, GPIO3 are four GPIOs are 32-bit GPIOs
I gave this up, as computer will freeze as in the the previous section.
11. Demo 6 : Thermal Management, Finite Element Analysis & Computational Fluid Dynamics
Description
From my Blog 5, (2.6 Ultra96-V2-G Finite Element Analysis & Computational Fluid Dynamics) - I have made heatsink model in FEA/CFD MultiPhysics (old version), which is not fully realistic. It is as such complete to run simulation. By realistic, I mean adding 161 SMD capacitors, SMD resistors of different sizes , 20 -30 inductors, some ICs. This will take time (and/or paid work) and may be I should not make realistic as it will crash with this small pc & it will need 5-7 days running time.
Some of the model pics, which is used in simulation
Fan
Fan with Connector
The heatsink in Ultra96V2-G is an active heatsink, not passive heatsink.
For thermal management, pls see my research paper - Analysis of Thermal Management and Cooling DC Fan of Ultra96-V2-G Multi Processor Single Board Computer.
There are two studies - stationary study and time dependent study. In stationary study, there is a steady-state condition with all parameters constant. In time dependent study, parameters change with time.
The simulation results of this model(which will get modified) are below :
1) Result 1 : This is the result of Stationary Study
The data generated is uploaded in Files Menu as Dataset 1
2) Result 2 : This is the result of Time-Dependent Study.
This took 10 -12 hrs computation time
The data generated is uploaded in Files Menu as Dataset2
12. Failed Demonstrations
Besides above mentioned, you can see below I was preparing, Time constraint is also big factor, when much of the time synthesis and two software and personal works
12.1) Mobile Wifi, Bluetooth & Android Applet
I am a registered android developer (basic not advanced in java) and have developed Android applets, even uploaded on google play store but now removed from store. As Ultra96V2G has wifi chip - ATWILC3000-MR110CA, I wanted the sensor data on my phone Due to time constraint , I gave this up.
As per the manual, supports linux kernal only upto 5.15
But if the wifi driver is updated with version 16.1, Ultra96V2G will support even linux kernal 6.1. So, 2 possible kernals are mentioned 5.15 and 6. 1
As mentioned in the blog 1, during initial installation in the video Series: AMD Xilinx Zynq Ultra96-V2, Part- I, I had used kernal verson 5.19.0-41.
I updated linux-version 6.1 and 6.2 but both versions were making usb mouse stop working, so I am now using 5.19.0-50.
The Wi-Fi worked without any separate upgradation of any wifi driver in the Ultra96V2-G SBC.
The onboard chip is ATWILC3000-MR110CA which has frequency range between 2.412GHz - 2.472GHz (2.4GHz ISM Band) and the radio is IEEE 802.11 b/g/n compliant for up to 72 Mbps PHY rate.
12.2) Keypad, Click Mezzanine and LCD Mini Click
12.3) Keypad, Click Mezzanine and LCD (older type)
12.4) LMS6DSL was not detected from the beginning and still remained undetected.
From my blog 4,
I tried like in LCD mentioned below c++ code but all failed
LSM6DSLSensor::LSM6DSLSensor(SPI *spi, PinName cs_pin, PinName int1_pin, PinName int2_pin, SPI_type_t spi_type ) :
_dev_spi(spi), _cs_pin(cs_pin), _int1_irq(int1_pin), _int2_irq(int2_pin), _spi_type(spi_type)
LSM6DSLSensor::LSM6DSLSensor(DevI2C *i2c, uint8_t address, PinName int1_pin, PinName int2_pin) :
_dev_i2c(i2c), _address(address), _cs_pin(NC), _int1_irq(int1_pin), _int2_irq(int2_pin)
int LSM6DSLSensor::get_x_axes(int32_t *pData)
int LSM6DSLSensor::get_g_axes(int32_t *pData)
int LSM6DSLSensor::get_x_sensitivity(float *pfData)
int LSM6DSLSensor::get_x_axes_raw(int16_t *pData)
int LSM6DSLSensor::get_x_odr(float* odr)
int LSM6DSLSensor::set_x_fs(float fullScale)
int LSM6DSLSensor::enable_free_fall_detection(LSM6DSL_Interrupt_Pin_t pin)
int LSM6DSLSensor::get_step_counter(uint16_t *step_count)
int LSM6DSLSensor::enable_tilt_detection(LSM6DSL_Interrupt_Pin_t pin)
13. Demo 7 : Zynq Ultrascale+ I2C, GPIO, Sleep,Reset and U-Boot
Description : Putty and G2K Linux Commands Video Demo
From Product Change Notification PCN19003, U20 Regulator change from 0.9V to 0.85V
1) Video I2C
2) Video GPIO
3) Video Sleep, Reset and U-Boot
14. Demo 8 : LCD MiniClick
Description
Backlight Control & Contrast Adjustments by Onboard MCP23S17 port expander, MCP4161 digital potentiometer, PWM pin of SPI Interfaced LCD Miniclick
In my blog 4, I had mentioned " ... I checked the code now gives no error but brightness from 0 to 9 , not showed even in darkness! Brightness level remained same. May be with text it show brightness. ..."
In this final, I have corrected it and 2 videos are proof. Mistake was SPI controller and LCD code has to be written in c++ like mentioned in training manual.
Following functions were made in C
Interrupt handler, void PWMIsr(void *InstancePtr) void PWMIsr(void *InstancePtr) int SetupInterrupSystem() void printCharacters(char8 *command, s32 commandBytes) void changeBrightness(char8 *command, s32 commandBytes) void changeContrast(char8 *command, s32 commandBytes) void changeVisibility(char8 *command, s32 commandBytes) void clearDisplay() void displayOn() void displayOff() void changeDisplay(char8 *command, s32 commandBytes) void returnHome() void cursorOn() void cursorOff() void cursorBlinkOn() void cursorBlinkOff() void setCursorPosition(char8 *command, s32 commandBytes) void changeCursor(char8 *command, s32 commandBytes) void displayCommands() s32 readCommand(char8 *command, s32 maxBytes) void processCommand(char8 *command, s32 maxBytes)
Snippet SPI c++
int SPIController::initialiseController() int SPIController::sendData(u8 slaveSelect, u8 opcode, u8 address, u8 dataByte) int SPIController::sendData(u8 slaveSelect, u8 opcode, u8 address, u8 *dataBuffer, u8 dataLength) int SPIController::sendData(u8 slaveSelect, u8 *dataBuffer, u8 dataLength) int SPIController::writeToSlave(u8 slaveSelect, u8 *writeBuffer, u8 dataLength)
Snippet LCD code in c++
int LCDMiniClick::initPWM(u32 pwmBaseAddress) int LCDMiniClick::changeBrightness(u8 period) int LCDMiniClick::changeContrast(u8 contrast) int LCDMiniClick::clearDisplay() int LCDMiniClick::returnHome() int LCDMiniClick::cursorOn() int LCDMiniClick::cursorOff() int LCDMiniClick::cursorBlinkOn() int LCDMiniClick::setCursorPosition(u8 row, u8 column) int LCDMiniClick::displayOn() int LCDMiniClick::displayOff() int displayCharacters(u8 *dispChars, u8 numChars) int LCDMiniClick::configurePortExpander() int LCDMiniClick::configureLCDDriver() int LCDMiniClick::configureFunctionSet(u8 configuration) int LCDMiniClick::configureEntryMode(u8 configuration) int LCDMiniClick::sendInstruction(u8 instruction, u16 delay) int LCDMiniClick::sendCharacter(u8 character) int LCDMiniClick::writeLowNibble(u8 value, u8 rsState) int LCDMiniClick::writeBothNibbles(u8 value, u8 rsState) int LCDMiniClick::sendByte(u8 expanderRegister, u8 dataByte)
Below are 2 video proofs
Video : LCD1
Video : LCD2 GTKterm
14. Demo 9 : 2 LEDs controlled by PWM/Interrupts Click Mezzanine
Description : 2 LEDs controlled by PWM/Interrupts Click Mezzanine without need of resistance but software controlled by dimmer
Below is burnt LED as code earlier failed
15. Pump, 2 Soil Moisture Sensors
This is failed as mistake in connection & coding incomplete and I m sleepy and time is up. Soil moisture sensors got powered on and connected to Analog pins of Click Mezzanine.
I can try but it is ricky, this is powerful pump, can give shock or damage board.
So many things failed and it will take time with FPGA, but as the main objective of this program is to build even a graduation project, I have shown quiet a number of demonstrations when I m completely new in FPGA and may be a single custom IP may be sufficient. The left out things may be shown in future.
16. Suggestions to Update DataSheet and Training
1. In Ultra96-V2 Product Brief, the datasheet should mention in related parts or accessories, the type of cables need to be bought with pics (this saves double triple time market visits). At the begining of training, cable view was not clearer..
- JTAG Cable
- Cable from Ultra96V2G to PC/Laptop/Computer
- Display Port cable
- High speed Expansion Cable
- USB to I2C click cable
Three of the above cables except High speed Expansion Cable, is mentioned in Ultra96 Accessories. These cables are not even mentioned in Ultra96_Accessories_201210.pdf and not even in brochure.
Some have privately criticised me- why showed cables in my blog2, explained plugs etc. It is my blog, I have mentioned whatever I felt important and can be publicly submitted internationally. And here I m even suggesting it as an update to their datasheet. Now on last day, I wanted to use JTAG cable, on USB to I2C click cable but it is of different size.
2. The datasheet though of Ultra96-V2 works well for this board Ultra96-V2-G, the datasheet can add this board as Ultra96-V2/Ultra96-V2-G or separate datasheet can be released.
3. The heatsink type is different. Heatsink mentioned in some AES Ultra96-V2-G brochure is not passive heatsink, it is an active heatsink.
17 . Path Programmable 3 Journey & Summary
The college students, interns (and now even school students) who get opportunity by this learning way, I in my 40 years got first time. I was not allowed to take FPGA training as I'm not btech.
Thanks to Element14/Newark/Farnell/Avnet for conducting Path programmable, sponsor AMD and then choosing & allowing me as international challenger and participant in individual,solo category(not representing anyone else).
I m happy that despite lot personal problems, I was able to submit all 5 blogs on the earlier deadline date, and even submitted this final blog.
I am also happy that I am able to submit this Final project blog with demonstrations and 4 Custom IPs.
Below is the list of 5 blogs :
- Blog 1 : Introduction & Software Installation
- Blog 2: Received Challenger's Kit, Kit Description, Licensing & Connectivity
- Blog 3 : Combat Training Beast FPGA MPSoC Hardware Lab
- Blog 4 : Combat Training Beast FPGA MPSoC Software Lab
- Training Final Blog 5 : AES-ULTRA96-V2-G FPGA MPSoC
I have written some preprint papers, mentioned in blog5. A new research paper - Analysis of Thermal Management and Cooling DC Fan of Ultra96-V2-G Multi Processor Single Board Computer. Some are still incomplete will take time and may be uploaded later.
I also participated in Forum. Some of the Explicitly mentioned participation's are below, other problem faced or solved are not mentioned explicitly.
- Board shipment Delay
- Solved:Files Upload Question
- Solved:Linux/Ubuntu Installation stuck in Vivado/Vitis AMD
- Solved:Free Vivado Design Edition License
- Solved:Bootable MicroSD for AES-ULTRA96-V2-G
I even made dedicated You Tube Channel Series but they are meant for proof purpose only , of work done and the proof that I did not sat idle, has worked, not copied from others. So these are meant as proof and one need not go on youtube channel. All videos are uploaded in blogs.
Synthesis
From the training and initial installation, the linux kernal changed to 5.19.0-50-generic from 5.19.0-41-generic. I had tried kernal version 6.1, 6.2 but due to some problem in USB, I rolled back to this 5.19.0-50-generic.
The most irritating thing in Vivado 2023.1, I found is synthesis. Running it do not take 30 min but hours time. I modified and it took 24hrs and was still running. It consumed lot memory, sometimes when left, computer/pc freezed after hours. And it crashed pc several times. At this time of updating on 31 Aug/1st sept, 2023, vivado synthesis still running for 16 hrs. Now, I m re-installing it, which takes in itself too much time. I re-generated licence online from AMD website. I rolled back kernal version from 5.19.0-50-generic to 5.19.0-41-generic but ubuntu gave error, so again installed kernal 5.19.0-50-generic. One week wasted in this synthesis, that too on the last crucial submission. Also, got problem mentioned in forum urgent bug correction.
This synthesis was headache,annoying as I cannot generate bitstream without it and was hindrance in testing my custom IPs- ILA_pwm v2, ILA_adc.
If I run synthesis in IP, it completes in 20-30 min. But if I add this IP or even not IP, it takes hours- 9hr, 16 hr, and running. So, the custom IP demo is shown in simulation, vivado simulator, and its synthesis.
I have made 4 custom IPs (Not in Repository) which are submitted and 3 incomplete IPs, which I would be using in the future for personal R&D. I have designed ILA_pwmv1 and ILA_pwmv2 The PWM and ADC channels are limited but I have written in software code, daisy chain algorithm but I have 2-3 more code modification ideas to test it practically. Some of the related papers like in AES, SHA,Elliptic curve, hyperelliptic curve , Galois counter mode, CortexR4 may be submitted.
Training
Regarding the training, I had already mentioned in blog 3 and blog 4
" ... I liked videos as they were short and in these lessons I got what Ultra96V2 is. I really didn't wanted to go through long lessons. ..."
And here on training page, I had written in feedback/comment
" Liked as short and gives idea of what ultra96 is. Beginners or Freshers will need more content."
I completed my training on 2023.1 with study material of 2021.1/2021.2. I had submitted proofs of these in Blog 3 and blog 4. I have brought out differences in software's, libraries with few new differences found while doing this final project blog.
The training was sufficient to make me understand to self-explore AES-Ultra96V2G board completely and I have shown its exploration in blogs and in this final project blog. I have explored in multi-disciplinary and successfully demonstrated non-copied work.
I even understood how to write VHDL/Verilog programming as I have demonstrated it above in Customized IPs.
I learnt TCL scripting and even demonstrated above. I demonstrated RTOS coding handling, linux handling.
Many btech can easily criticise and even I can criticise their work. I have not claimed some expert level or advanced & they will get a job with graduation build up which I have shown in this blog but not me.
I learnt FPGA , multi-core processor on which also I have shown here some demonstrations.
Suggestion For Future
I have mentioned this feedback and suggestion on A Good Reason to Read the element14 Community's Terms and Conditions and even this got discussed with Mr. Randall, here repeating.
1) This is 64-bit processor. Time duration to build project on these 64-bit should be increased from 30 days to 45 days or 60 days, for a graduation project.
One is the complexity but many will still do basic projects, the other reason for increase of time is it is 110.8 GB software which takes time to download, time to unzip, uninstalling 230 GB and installing. My computer (linux) has crashed completely 2-3 times.
There are two software's- Vivado and Vitis and they generate common errors, leaving the mistake in verilog or VHDL or software c++/c coding. Addition of external software like MATLAB, PLECS, Altium, COMSOL, ANSYS,FLOWTHERM takes extra time.
For example, I have designed custom IPs and I can attach these mentioned software's and show more technical proofs.
2) As I m hobbyist or may be professional engineer, I have goal of building my innovation project which need months time. Separate complex projects build up can be given 4-6 months but e14 has its goals.
Or from this final selection stage or for this particular contest only, who willing or selected by sponsor or e14, can sign up for advance completion because my work would need 6-18 months time or so. But I will then have to file patent also if successful and may need 1 more board (any MCU) or your company/sponsor/partner can hire me!
3) Never put mandation of team requirement (otherwise an individual like me could never apply).
4) Never put mandation of professor or mentor or supervisor (otherwise an individual like me could never apply).
5) For enrolment never put degree, diploma, age, marks condition (otherwise an individual like me could never apply).
6) FPGA is very complicated and I found it requires c++ also. So, some c++ example like taught in colleges or paid interns should be given.
7) Even though material did taught and I learnt, but when I tried to make complex project, I feel some concepts I am still missing but I might find it out later.
Though I have left R&D (after long struggle, I also succumbed) but as stuck due to personal papers and personal r&d, employers who wiling to pay, can contact for remote/hybrid project/consultancy. As this personal R&D goal is still left, I hope to get selected in future design/road challenges & work on paid project.
Abhishek Bansal
(Not representing anyone else.Category:Individual)
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