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XXICC (21st Century Co-design) release 0.0q

johnbeetem

Release 0.0q has been replaced by: XXICC (21st Century Co-design) release 0.0r

 

Here is the new release 0.0q of XXICC.  0.0q adds logic capacity to Flavia implementation and allows you to specify pull-up, pull-down, and keeper circuits for FPGA I/Os in all implementations.  The Flavia architecture is now more consistent across all implementations: see the Flavia chapter of The XXICC Anthology rev 0.0q which has an updated version of Flavia: the Free Logic Array.


XXICC (21st Century Co-design) is a not-for-profit research project which attempts to bring digital hardware/software co-design into the 21st Century using an improved programming language and a Reduced Software Complexity philosophy.  Its goal is to make it easier and more enjoyable to write and maintain digital hardware and software. XXICC is pronounced "Chicken Coop", so-called because it has so many layers.

 

For an overview of XXICC, see XXICC: 21st Century Co-design.  For details on the GalaxC programming language, XXICC Object Editor, and GalaxC extensions for Hardware Design (GCHD), here are the latest documents and source code:

 

Release notes for XXICC rev 0.0q

Programming in the GalaxC Language rev 0.0j: reference and user guide for the GalaxC programming language, unchanged for 0.0q.

The XXICC Anthology rev 0.0q: collection of miscellaneous XXICC topics, including user guides for the XXICC Object Editor, GCHD and Flavia.  0.0q has a major rewrite of the Flavia chapter (12).

XXICC code release 0.0q: all source code for XXICC.

XXICC source code listing rev 0.0q: source code listing as PDF.

XXICC executable binary for Windows rev 0.0q: XXICC executable binary for Microsoft Windows.

GalaxC sample/demo programs rev 0.0k: sample GalaxC programs and GCHD logic libraries, unchanged for 0.0q.

GalaxC sample/demo program listings rev 0.0k: PDF listing of the sample GalaxC programs and GCHD examples, unchanged for 0.0q.

Installing and Running XXICC rev 0.0q: Document describing how to install and run XXICC.

Compiling and Running GalaxC Programs rev 0.0k: Document describing how to compile and run your own GalaxC programs, unchanged for 0.0q.

Editable XXICC documentation files rev 0.0q: editable XOE files for XXICC documentation.

Data files for FlaviaP40 release 0.0q for Papilio One 250K: Data files for the FlaviaP40 implementation of the Free Logic Array.

Data files for FlaviaP60 release 0.0q for Papilio One 500K: Data files for the FlaviaP60 implementation of the Free Logic Array.

Data files for FlaviaPD59 release 0.0p: Data files for the FlaviaPD59 implementation of the Free Logic Array for the Papilio DUO, unchanged for 0.0q.

Data files for FlaviaLP60 release 0.0q for LOGI-Pi: Data files for the FlaviaLP60 implementation of the Free Logic Array for the ValentF(x) LOGI-Pi.

Data files for FlaviaLB60 release 0.0q for LOGI-Bone: Data files for the FlaviaLB60 implementation of the Free Logic Array for the ValentF(x) LOGI-Bone.

Taming the Wild Bitstream (unchanged for 0.0q): Supplement to Flavia: the Free Logic Array.

 

I've tested XXICC 0.0q on GNU/Linux (Ubuntu on x86 PCs, Raspberry Pi Raspbian, BeagleBone Debian, and ODROID-C1 Ubuntu) and Windows (2000 and 7).  My main machine is Ubuntu, so the others are more likely to have anomalies.  Constructive comments and suggestions are most welcome.  I'd especially like to find out how to reproduce some of the bugs that have been eluding me.

 

The previous version of XXICC is: XXICC (21st Century Co-design) release 0.0p

The earliest versions of XXICC are at Google Code: code.google.com/p/xxicc/

 

XXICC is a FLOSS (Free as in Liberty Open Source Software) project.  Software is licensed under GPLv3 and other content is licensed under Creative Commons CC-BY-SA 3.0.

  • XXICC Issue #27

     

    There's a GCHD bug in XXICC 0.0p and 0.0q involving conditional updates of registers.  Here's some sample code that exposes the bug:

     

        if !reset then {s3 = s2 = FALSE; s1 = s0 = TRUE} else

        if clk rises then

        { // On rising clk, increment s3-s0 if "up", otherwise hold s3-s0.

          s3 ^= up & s2 & s1 & s0;

          s2 ^= up & s1 & s0;

          s1 ^= up & s0;

          s0 ^= up;

        };

     

    Compiling this produces the message "Register update must follow standard form" on the line "s1 ^= up & s0".  If you try recompiling GCHD it goes into an infinite loop.

     

    The problem is that XXICC 0.0p and 0.0q do not like an expression like "!reset" as an if-then-else condition.  GCHD works fine if you first assign "!reset" to another net and then use that net name in the if-then-else, so use that work-around for now.

     

    The bug was introduced in XXICC 0.0p when I changed NOPSAs to LOADSAs (see the 0.0p release notes).  The bug fix was easy and will be incorporated in XXICC 0.0r.