I've been following the discussions about the VIDOR4000 in the FPGA group. There was a giveaway associated with the Webinar but of course there will be sonme disapointed non-winners.
If you want to get into playing with FPGAs one of the cheapest routes I've found so far is to buy a simple dev board from Aliexpress. There are lots avaialble but this blog is about the Cyclone 10
board from QMTech.
I paid about £16 for mine. I already have a "ByteBlaster" programmer but if you don't it will cost about another £10.
The free version of Altera Quartus will do for development.
The Cyclone 10 FPGA on this board is smaller than the one on the Vidor board with only about 6k logic elements - but that's enough for useful work.
The board has a 50MHz clock oscillator, a boot Flash chip and a 32MByte SDRAM and the usual regulators for the supply. It comes with a resaonable set of examples which are
extermely useful in getting it running. I downloaded Version 17.1 of Quartus from Intelto match the version used on the board examples. I've also downloaded the 20.1 version for
my own stuff. Running FPGA designs on different versions of the tools often causes problems - so it's best avoided if you can.
The examples are all in Verilog.
There's a good blog from jc2048 at VIDOR 4000: Servo Interface where we have had some discussions about VHDL coding (style and substance 
) and a thing that came up
was the possibility of using standard VHDL to infer Block Rams on the FPGA. (The other way is to explicitly refer to the block ram using special IP blocks specific to the FPGA vendor).
Having got the LED flasher Verilog demo translated to VHDL I've added a chunk of RAM to the design. It doesn't have anything to do right now so to stop the tools optimising it away
I've connected it to pins. (Which takes me to another big virtue of the QMTech board, it has about 100 IO pins available on its headers.)
This a block diagram of the project. It's done in Aldec-HDL. It's a complete VHDL/Verilog simulator (and more). The block diagram automatically makes all that boring VHDL or Verilog
that links blocks together. The actual code is inside the blocks. I find it helps a great deal to visualise a complex project and saves a lot of time. It isn't free.
This is the RAM code:
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
entity mem_inf_sp_64_12 is
port(
we : in STD_LOGIC;
en : in STD_LOGIC;
clk : in STD_LOGIC;
address : in STD_LOGIC_VECTOR(5 downto 0);
data : in STD_LOGIC_VECTOR(11 downto 0);
q : out STD_LOGIC_VECTOR(11 downto 0)
);
end mem_inf_sp_64_12;
--}} End of automatically maintained section
architecture mem_inf_sp_64_12 of mem_inf_sp_64_12 is
type ram_type is array (0 to 63) of std_logic_vector(11 downto 0); -- array must be 0 - n, if declared the other way wit downto to match Xilinx example then Quartus fitter fails
signal ram : ram_type;
begin
process(clk)
begin
if rising_edge(clk) then
if en = '1' then
if we = '1' then
ram(to_integer(unsigned((address)))) <= data;
end if;
q <= ram(to_integer(unsigned((address))));
end if;
end if;
end process;
end mem_inf_sp_64_12;
All pure VHDL but note that comment on line 21 - my Xilinx example codes the array "63 downto 0" - I don't have a Xilinx toolset runing so I can't test if they care, but the Altera tools
only infer the block memory one way round.
(There seem to be some extra brackets in lines 31 and 33 - but they do no harm)
The screenshot shows the loveliness of the Altera toolset and the resources used
So there you go - a really cheap (and by FPGA standards, a quite simple) way into FPGA.
QMTech do a very similar board (but about twice the price) with an Artix 35 on it - I'll attempt to repeat this experiment when it turns up.
MK
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