How to use Vitis HLS IP in Python Pynq overlay Environment.

Hello everyone,

happy new year. Please guys can you help me to fix my problem. I have programmed a HLS IP for using in vivado to transfer data from PL to PS. I am using pynq overlay. When i start the IP by writing in the register of the custom ip (0x0, 1) then i cannot write anymore in the same register (0x0, 0) can please someone help to understand why how can i fix it. Thank you very much.

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flyingbean over 1 year ago +1

I have not done Vitis HLS/Pynq Overlay before. From my reading at Xilinx website, you need to update HLS IP with the FPGA bitstream first, then use Phyq Overlay to load the updated FPGA bitstream second…
Jan Cumps over 1 year ago in reply to flyingbean +1

I've tried some HLS/Pynq combinations before. Checking if I can find my blogs back ... edit: found: Learning Xilinx Zynq: Try to make my own Accelerated OpenCV Function - 1: Vitis HLS (failed…

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flyingbean over 1 year ago

I have not done Vitis HLS/Pynq Overlay before. From my reading at Xilinx website, you need to update HLS IP with the FPGA bitstream first, then use Phyq Overlay to load the updated FPGA bitstream second. I believe that you need to reset PL from PS side without powering off the FPGA. If your updated FPGA bitstram has no bugs, you can get things work as you expect.
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Jan Cumps over 1 year ago in reply to flyingbean

I've tried some HLS/Pynq combinations before. Checking if I can find my blogs back ...

edit: found:

Learning Xilinx Zynq: Try to make my own Accelerated OpenCV Function - 1: Vitis HLS (failed attempt)

Learning Xilinx Zynq: Try to make my own Accelerated OpenCV Function - 2: Vivado Block Design (failed attempt)

PYNQ and Zynq: the Vitis HLS Accelerator with DMA training - Part 1: Turn C++ code into an FPGA IP

PYNQ and Zynq: the Vitis HLS Accelerator with DMA training - Part 2: Add the Accelerated IP to a Vivado design

PYNQ and Zynq: the Vitis HLS Accelerator with DMA training - Part 3: Use the Hardware Accelerated Code in Software

PYNQ and Zynq: the Vitis HLS Accelerator with DMA training - Deep Dive: the data streams between Accelerator IP and ARM processors

flyingbean over 1 year ago in reply to Jan Cumps

Hi Jan: I will reproduce PHYQ projects you published soon. It is on my to-do-list for 2024.
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flyingbean over 1 year ago in reply to Jan Cumps

Hi Jan: I will reproduce PHYQ projects you published soon. It is on my to-do-list for 2024.
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