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Blog PYNQ and Zynq: the Vitis HLS Accelerator with DMA training - Part 1: Turn C++ code into an FPGA IP
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  • Author Author: Jan Cumps
  • Date Created: 26 Nov 2021 9:03 AM Date Created
  • Views 4145 views
  • Likes 3 likes
  • Comments 3 comments
  • vitis_hls
  • vivado
  • hardware_accelerators
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PYNQ and Zynq: the Vitis HLS Accelerator with DMA training - Part 1: Turn C++ code into an FPGA IP

Jan Cumps
Jan Cumps
26 Nov 2021

PYNQ now supports Vivado and Vitis HLS version 2020.2 (since PYNQ 2.7).
Time to re-check  the hardware accelerator mechanisms, with DMA. This workflow has now stabilised.

Hardware Acceleration is the technique to implement program logic inside the FPGA. It will become a set of logic blocks, instead of a set of machine instructions in executable memory.
The logic is written in a programming language, in this case C++. Vitis HLS  will turn this into HLS (you can choose if it's VHDL or Verilog, but that's not important).
Typically, you'd select a block of code that is too resource-heavy on your processor. You copy that code into a Vitis HLS project, define how the interfaces in an out will be done, and let it build.
The build will generate an IP that can be used in Vivado like any other IP. THere you add it to your hardware design.
Once you load the resulting bitfile into the Zynq, you can call this code from your program. In effect, you have now turned a bottleneck logic function into a hardware process.

I'm following the 3-part using a HLS stream IP with DMA training on the PYNQ community. This blog will not repeat the steps. The goal is to document the experience.

Prepare a C++ function for hardware acceleration

The source code is a bit different, but you'll recognise that it's common logic.

#include "ap_axi_sdata.h"
#include "hls_stream.h"

void example(hls::stream< ap_axis<32,2,5,6> > &A,
	     hls::stream< ap_axis<32,2,5,6> > &B)
{
#pragma HLS INTERFACE axis port=A
#pragma HLS INTERFACE axis port=B
#pragma hls interface s_axilite port=return

	ap_axis<32,2,5,6> tmp;
    while(1)
    {
	A.read(tmp);
	tmp.data = tmp.data.to_int() + 5;
	B.write(tmp);
     if(tmp.last)
     {
         break;
     }
    }
}

There are predefined patterns. The inputs and outputs have to be selected from a set of types. There are primitive types and containers.
In our example, we'll use hls::stream for input and output.
The demo function reads the stream of integers. Then it adds 5 to each value and writes that sum to the output stream.
In the real world, this could be something else like image manipulation, FFT transformation, filtering, compression, CRC calculation, en/decryption...
That's it.

image

image: FPGA resource cost of the generated IP

Accelerators are most useful in scenarios where data can stream. It's not your solution if OS resources are needed, such as access to files.
They work good together with DMA.

After a successful build, Vitis HLS will summarise the FPGA resource cost. It will also show the interfaces.

image

image: interface definition and possible performance warning

It will also generate the IP package that we'll use in the next post, to integrate it in a Vivado flow. The next step to make this function callable from software.

image

 

Pynq - Zync - Vivado series
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Learning Xilinx Zynq: port Rotary Decoder from Spartan 6 to Vivado and PYNQ
Learning Xilinx Zynq: FPGA based PWM generator with scroll wheel control
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Learning Xilinx Zynq: Try to make my own Accelerated OpenCV Function - 1: Vitis HLS
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PYNQ version 2.7 (Austin) is released
PYNQ and Zynq: the Vitis HLS Accelerator with DMA training - Part 1: Turn C++ code into an FPGA IP
PYNQ and Zynq: the Vitis HLS Accelerator with DMA training - Part 2: Add the Accelerated IP to a Vivado design
PYNQ and Zynq: the Vitis HLS Accelerator with DMA training - Part 3: Use the Hardware Accelerated Code in Software
PYNQ and Zynq: the Vitis HLS Accelerator with DMA training - Deep Dive: the data streams between Accelerator IP and ARM processors
Use the ZYNQ XADC with DMA part 1: bare metal
Use the ZYNQ XADC with DMA part 2: get and show samples in PYNQ
VHDL: Convert a Fixed Module into a Generic Module for Reuse
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  • Jan Cumps
    Jan Cumps over 3 years ago in reply to Jan Cumps

    Xilinx is preparing a workaround and a patch.

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  • Jan Cumps
    Jan Cumps over 3 years ago

    Warning if you're using Vitis HLS. The platform is impacted by a Year2022 bug: https://support.xilinx.com/s/question/0D52E00006uxnnFSAQ/2022-timestamp-overflow-error-2201011128-is-an-invalid-argument-please-specify-an-integer-value?language=en_US

    TL;DR: you need to set the clock to a 2021 date to build a design. All recent Vitis HLS versions are affected.

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  • Jan Cumps
    Jan Cumps over 3 years ago

    The generated IP block contains the VHDL and Verilog source.
    This source should not be edited and isn't intended for human consumption. Her's a snippet anyway:

    constant ap_const_lv32_5 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000101";
    --
    B_TDATA_int_regslice <= std_logic_vector(unsigned(A_TDATA_int_regslice) + unsigned(ap_const_lv32_5));

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