Read this for info only. The project done at the time didn't work. I'm leaving the blog here as a testimonial that things have become easier and more streamlined with the 2.7 release of the example.
It works, and can easily be repeated, with Vitis HLS and Vivado 2020.2, on PYNQ 2.6 and 2.7.
There is an example project that shows how to run OpenCV functions in FPGA instead of on a processor.
This practice of off-loading heavy processing from software in the processor to hardware designs running inside the FPGA fabric is called hardware acceleration.
I reviewed it here: Learning Xilinx Zynq: Hardware Accelerated Software.
In this series, I will try to do the same, with the 2020.2 toolchain and sources.
Part 2: Take the Vitis HLS IP from Post 1 and configure the Block Design
I created a project called accelerate_vision, using the script from Automate Repeatable Steps in Vivado.
That results in a Block Design with a number of the IPs placed and preconfigured.
Reconfigure the IPs
Enable the two PS - PL interfaces Master AXI GP0 and Slave AXI HP0
Leave all other settings like they were created by the TCL script.
Delete it. It's not used in this design.
Add an additional Master interface
Add new IPs
The Vitis HLS Resize Hardware Accelerator
This is the block we created in the previous post. Make it available for this project.
In Project Manager -> Settings, go to the IP Repository screen, and click the +.
Add the location of the Vitis HLS project from that previous post.
Vivado will tell you that one new IP is available for your design. Your resize_accel.
Navigate to the Block Design screen, click the +, and add the IP to your design.
Here I'm stuck - the Xilinx example builds an AXI Master interface. The HelloWorld example uses AXI Lite. I have to study ...
I have altered the Vision resize example code to adapt use AXI Lite as interface instead of AXI Master. The previous blog is rewritten to reflect that.
When I fully understand the AXI mechanisms, I may revisit this...