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  • Author Author: Jan Cumps
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Programmable Electronic Load - Analyse the Summing Node Zero Point

This blog documents investigates the feedback node of the electronic load that , and are designing.

It's an important spot in the load's design. It measures the set point and the feedback from the output.

When the output is driven to 0, it should be on a potential as close as possible to 0 V.

On the first prototype it's -0.2 V. Not so much off, but the negative value  influences our ADC measurements.

This document checks how we can get this node to 0 V.

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Because this document is evolving, some comments below may be out of sync with the content. That's because the content is adapted based on the conversation.

The measurements taken here are based on the original design, without R32 in place and U3B + tied to ground.

The current sense side of R7 is connected to ground, and a variable negative voltage from 0 V down is applied to the current sense side of R8 to simulate current being sensed.

 

The circuit isn't complex. The set point is driven by a DAC. It's set to 0 for this test.

The second input to this node is OpAmp 3C. It has both inputs tied to ground so should theoretically have 0 V at the output.

On my board I measure a potential of -0.212V at the left side of R33.

I hope to get this closer to 0 V to ease the ADC a bit - its performance degrades with negative voltage at its inputs.

Like the other blogs for the electronic load, this is a working document that will be updated with findings from anyone who wants to chime in.

 

Behaviour at 0V

 

buzy image

  • in reply to Jan Cumps

    When I shortcut the DAC1 output, I get almost the same as when the output is off. So it seems that the offset is caused by offset of the DAC.

    image

     

    When driving the DAC to 0, I get 0.731 mV output. The measured voltage over the sensor resistor is then 0.054 mV.

    If I shortcut DAC A, I measure 0.005 mV over the 0R05 sense resistor. That's virtually the same as INPUT OFF (0.003 mV).

     

    I'll have to check if I can deal with the positive DAC offset ...

  • in reply to Jan Cumps

    I've been checking for a while and get 0.6 µA when measuring with a multimeter. I usd a fairly high input voltage of 14 V to compensate for any cable resistance.

     

    image

  • I'm going to redo this exercise now that the OpAmps are replaced with lower bias ones and I have more precise measurement tools.

    From the blog Programmable Electronic Load - LabVIEW Test Automation: Characterise the Instrument we can see that the behaviour is very linear.

    But we have a non-0 start point. When th DAC is driven to 0, there is an output current flowing of a few mA.

    image

    I assume that it's our control circuit that's doing that, because if I disable the output (pull the gate to ground), the current that flows is neglectable. And it's the same FET that's fully blocking the current flow then.

     

    I've re-stacked the load so that the control board is on top and I have easier access to the measure point.

    I can't use the LCD display in that case. I'll use the SCPI interface to set values.

    image

     

    I'll measure DAC output and the voltages at relevant control circuit points to see what drives the FET to conduct a little.

    I think I'll document the results in new blog post. We can then think on measures to get the lowest current lower than 2 mA.

  • in reply to Jan Cumps

    Look at the temperature behaviour of the setup (power supply + eload):

    image

    I started sampling last night: 2074 * 6 measurements. Turned off the heat in the lab shortly after - that's when the slow ramp starts.

    This morning I opened the lab window and it's rather cold outside. You see a steep change at the end of the sampling.

  • in reply to Jan Cumps

    This is how a test cycle of 34 iterations looks like, filtered for a set voltage of 0.04 V:

    image

  • in reply to Jan Cumps

    The result of two cycles logged to an excel file.

    image

    The first column is the PSU output value, as set by the flow.

    The second column is the current that the load reports.

  • in reply to Jan Cumps

    Ah, simple data logging works too now. Just for one signal at the moment: the current measured by our load.

    image

  • in reply to Jan Cumps

    I have loops and logging working:

     

    image

     

    The program continuously steps through a given number of voltages.

    The voltage step increment and the number of steps are given as parameters. When the number of steps is reached, the flow starts over from 0V.

    image

    In this example the PSU is set to 0 V, 0.02 V, 0.04 V, 0.06 V and 0.08 V. It loops until you push the STOP button or when a VISA error occurs.

    image

  • in reply to jc2048

      wrote:

     

    If the input voltage is a bench PSU (sorry, I'm a bit slow to catch on at times), aren't you just measuring its noise.

     

    You've got a few millivolts of fluctuation in the readings at the output. Divide that by the gain of eight and that equates to something like half a millivolt at the input. You'd be lucky if your PSU was cleaner than that (particularly if it has a lot of automation stuff inside it).

     

    Anyway, do the test with lots of readings. It will be interesting to see if you get a scatter plot with a wide, fuzzy band stretching across it.

    Yes, definitely. I don't have the sense resistor or other power-side components yet.

    What I'm trying now is setting up repeatable measurements so that I have the learning curve behind me when the components arrive.

    I'm still learning how to loop and log in LabVIEW. Once I've mastered that, I'll try to do this exercise.

     

    One way to quickly test if you are measuring the PSU noise would be to put a larger resistor in series with the current sense resistor, scale up the voltages appropriately, and then see if the variation drops by the attenuation factor.

    I can't do that with a precision component - it's ordered but no info yet when my components arrive - but I have a few low-resistance-reasonable-tolerance through-holes components that I can use for this exercise.