Programmable Electronic Load - Analyse the Summing Node Zero Point

jc2048  wrote:

 

... The dip at 1.2V is a concern ...

I suspect that to be an operator error. I have to repeat all measures, in the same order, with properly probing, to be sure.

I don't see an obvious reason why opamps behave different at that particular value. Chances are fair that it's me ...

(or the ADC, because the measured values in the previous graph don't show the dip, only the ADC's volts value - I'm not satisfied yet with the stability of the ADC samples, they fluctuate somewhat per request...)

I haven't looked at the integrator's behaviour yet.

Taking only the 0 V offset in account, this is what I get when running the instrument at 0 A and 2 A:

0 A (Vsense == 0.000 V):

2 A (Vsense == 0.100V):

It might be easier to see what it's doing if you plot the difference between the expected and the measured. The dip at 1.2V is a concern - the rest looks like a positive offset of four or five millivolts, but there it reverses for some reason.

After this you're going to have to consider what you do with the bias currents of the integrator op-amp.

It gets very close if I compensate for the DC offset of the two opamps at 0 V input!

The blue line is uncompensated ADC

The dark purple one the expected (theoretical) value at ADC

The orange one the compensated ADC.

... it seems that each opamp introduces a 0.1 V offset. If that's the case, compensation should be doable. At least everything behaves linear

Some measurements (without any bodging, using the original schema.

I simulated the voltage over the sense resistor with a power supply. The input voltage is measured close to opamp 3C inputs - any setup resistance is compensated for.

In theory,

• UC3 out should be input * 7.8
• U3B out should be that value * -1
• ADC B should be the same (and is ) as U3B out

The ADC is behaving good. it closely reflects the actual voltage represented at its input.

The two opamps, both using non-precision resistors to set the gain, need compensation.

I've graphed it. For ease of understanding, I've inverted the negative Y values so that a trend can be seen.

• The X axis is the theoretical current as measured by a 0R50 resistor.
• The red line is the voltage over the sense resistor (simulated by a power supply, measured close to opamp 3C input), inverted
• The green line is the output of opamp U3C inverted,  it should reflect the X axis * -7.8 gain. It has a negative offset.
• The light purple line is the output of U3B. It's -3C multied by -1 (this one is off - it should be spot on - it has an offset).
• The light blue line is the output of U3B sampled by the ADC. I consider that "good enough" for the moment. Very close
• The dark purple line is what we should get at the ADC, if opamp and resistors were optimal.

Thoughts on compensation?

I've been studying up on the KiCAD schema editor some more, and was able to move the power part of the driver board to another sheet.

This gives some more space to draw the opamps and I've restructured the diagram a little.

It gives this view for the control loop and control feedback (edited picture to remove other components):

I haven't added the option to replace the U3B + direct to ground with a resistor (50K, 2 parallel 100K resistors) to balance inputs.

Let's see how your boards behave with or without these before adding them.

I'm continuing this exercise, to see what software calibrations are necessary.

At first glance, it looks like we have to at least compensate for these:

• the ADC has an offset when we push 0V to its input.
• to check what voltage appears on the output of U3B when there's a 0V drop over the sense resistor
• to check the real gain - theoretically it's * 7.8

Then check which of these are constant over the input range, which ones change depending on the voltage over the sense resistor.

The bad connections is or should be a one time issue during build, it should not occur after that

The issue comes up once the built in protection diodes start to conduct, aka about 250mV ish

jc2048  wrote:

 

Does it still affect the other ADC channels (going negative by only 5mV) or is it going to be usable in normal operating conditions?

 

...

The ADC seems to behave well up to at least -250 mV, and has errors on all channels when one input is below -700 mV. I haven't checked the in-between yet to find the tipping point - and haven't investigated the datasheet for this condition.

jc2048  wrote:

 

...

 

You've still got the problem with abnormal conditions - ie if someone connects the load output the wrong way round. Perhaps the way to deal with that would be to make it a 'perfect diode' circuit, though that wouldn't give you any warning that the output was connected wrongly.

 

...

Yes, I will have to test what situations can cause negative values on ADCs in normal conditions too.

jc2048  wrote:

 

...

 

 

5mV error is a bit better than 200mV, so it's a definite improvement (worth having for two extra resistors). But it's only 40 times better and substituting an op-amp with bias currents maybe a thousand times less would give much more benefit.

 

If you take a look at the datasheet above, you'll see that the voltage offset error is typ 0.5mV and may be more. Amplified by the 6.8 gain of the differential amplifier, that gives the potential for several millivolts of error at the ADC input. Saying it another way, the reduced bias current error is now around the same level as the voltage offset errors, which means, if you want to go further and try and make it even more precise, you're trying to work with (and disentangle) two error sources rather than just the one.

An exercise for the future or for someone who wants to improve the design - and certainly an interesting one.