Blog

  • The Art of FPGA Design - Post 18

    fpgaguru
    Using the Carry-Save Adder, A Generic Adder Tree In this post I will show how to implement an efficient and generic adder tree, we need to compute the sum of N elements, where N can be any value. The numbers we add are also arbitrary precision f...

  • The Art of FPGA Design - Post 17

    fpgaguru
    Using the Carry-Save Adder, Computing a Running Average I will show in the next few posts some design examples where using a 3-input carry-save adder instead of the normal 2-input ripple-carry adder makes a significant difference. The first exam...

  • Ultra cheap and Tiny FPGA Board

    michaelkellett
    This is  a little test board I'm putting together to experiment with the MAX32660 processor and the Lattice UP5K Ultra Plus FPGA. The UP5K is a tiny FPGA, available in a hand solderable 48 pin, 0.5mm pitch QFN with 5k LUTs, 15k bytes of...

  • The Art of FPGA Design - Post 16

    fpgaguru
    The Carry-Save Adder, two for the price of one This post is about buying two adders but paying only for one of them. When developing software the CPU and memory your code is running on is already paid for and there is little incentive to op...

  • The N64=>HDMI Conversion Project: Part 2

    muddpup64
    This is an update of my on going N64 HDMI conversion project. The N64=>HDMI Conversion Project As of right now I have identified that the RCP (or the GPU) have common outputs between board revisions for the video and audio. There is a seven bit wo...

  • The Art of FPGA Design - Post 15

    fpgaguru
    Counters, Adders and Accumulators One of the most common operation encountered in digital hardware design, especially for digital signal processing applications, is addition. This actually covers a large group of fundamental building blocks, lik...

  • The N64=>HDMI Conversion Project

    muddpup64
    This is a continuation of this post: Custom Vivado Parts/Board Creation and this post:Nintendo 64 Schematic   I plan on adding to this blog and over time creating a documented progression of the project. For those who did not take the ...

  • The Art of FPGA Design - Post 14

    fpgaguru
    The Universal MUX Building Block Part 3, the one with the Dutch Cocoa Box and the Ouroboros We have seen in the previous post that Vivado Synthesis is able to optimally infer a mux form behavioral code for multiplexers with up to 16 inputs, but ...

  • The Art of FPGA Design - Post 13

    fpgaguru
    The Universal MUX Building Block Part 2 So the question is now what is the most efficient implementation for arbitrary size multiplexers one should expect? If the result the synthesis tools infers from behavioral code is equal or very close to t...

  • Seven segment display controlled by Arty S7 board

    kk99
    I have a single seven segment display with common anode. This display has following symbol: FJS-5161B. Here is brief information from datasheet for this display:I have created a kind of PMOD module which contains a single seven segment display, eight...

  • The Art of FPGA Design - Post 12

    fpgaguru
    The Universal MUX Building Block The next example in the series of generic building blocks is a multiplexer. This is a combinatorial block - if we need pipelining we can always add that separately to keep it as generic as possible - with an inpu...

  • The Art of FPGA Design Series

    rscasny
    IntroductionThey may seem like an unlikely or odd couple: art and technology. Art implies the vast realm of unbridled creativity, while technology is bounded by empiricism: rules, standards and rationality. But when art and technology are interwoven,...

  • Integrating a Microchip Gigabit Ethernet PHY into the Xilinx FPGA Ecosystem - Hardware

    jafoste4
    Have you ever wanted to integrate a Microchip PHY into the Xilinx Ecosystem, but previously had no proven reference designs available to mitigate risk factors? Recently Avnet released the Network FMC (http://avnet.me/fmc-network1 ), which is a dual M...

  • The Art of FPGA Design - Post 11

    fpgaguru
    Instantiating LUT6 Primitives Part 2 Today I will show a couple of examples where LUT6 primitive instantiations make sense. To keep things short and simple these are somewhat artificial examples but situations like these tend to show up all the ...

  • The Art of FPGA Design - Post 10

    fpgaguru
    Instantiating LUT6 Primitives In the previous post we have already seen how to instantiate FPGA primitives, SRL16s in that case. The role of the synthesis tool is to take HDL behavioral code and translate it into a netlist of FPGA fundamental bu...

  • The Art of FPGA Design - Post 9

    fpgaguru
    The Universal DELAY Building Block Part 2, the one with the cake In the last post I have introduced an example of a universal delay block that uses a behavioral implementation to create a reusable module that can be used to delay a signal by an ...

  • The Art of FPGA Design - Post 8

    fpgaguru
    The Universal DELAY Building Block This is the first post in this blog in which I will try to actually design something useful based on the ideas introduced so far. Also, instead of just short code snippets, the code examples in this post are co...

  • The Art of FPGA Design - Post 7

    fpgaguru
    We're Not in Kansas Anymore In this post we will try to do things you probably never tried to do using VHDL, assuming they were not even possible in such a low level language. VHDL and Verilog/SystemVerilog are considered low level hardware...

  • The Art of FPGA Design - Post 6

    fpgaguru
    VHDL User Defined TypesNUMERIC_STD SIGNED is not a good choice for fixed point arithmetic Most signal processing applications require handling fixed point data types, not just integers. These numbers have a binary point, assuming we use binary o...

  • The Art of FPGA Design - Post 5

    fpgaguru
    Beyond STD_LOGIC In the last post we just started to scratch the surface of VHDL types. This time we will try to go deeper - which types should we use, what are their properties and limitations, what are the main pitfalls a beginner would encoun...

  • The Art of FPGA Design - Post 4

    fpgaguru
    What's Your Type? People new to VHDL usually come from a software background, maybe C/C++ or Java and might have a difficult time grasping the fundamental concepts of HDLs. VHDL in particular can be used as a sequential software language - every...

  • LPDDR4 timing parameters for Zynq UltraScale+ MPSoC in Vivado (Based on Ultra96)

    bhfletcher
    Note: The v1.0 Ultra96 board definition files (BDF) embedded in Vivado 2018.1 and 2018.2 have a bug. The latest BDF is on the Avnet GitHub here: https://github.com/Avnet/bdf . The article below describes the parameters included in the v1.2 board defi...

  • The Art of FPGA Design - Post 3

    fpgaguru
    Two Free VHDL Books If you installed Vivado WebPACK, the free version of Xilinx FPGA design tools, you are ready now to start creating your first hardware design. There are at least three different ways to program a Xilinx FPGA today, using a ha...

  • The Art of FPGA Design - Post 2

    fpgaguru
    Why learn FPGA Design? I have been asked in the comments why invest time and money to learn how to use FPGAs? First of all, if you are interested in advanced digital hardware design FPGAs are essentially the only game in town. Unless you are wor...

  • Implementing FFT Accelerators with SDSoC(TM) Using Open-Source Software and C-Callable IP

    drozwood90
    Hello all, I wanted to create a post letting everyone know about a new white paper that was generated by one of my colleagues, I have linked it below.  In this white paper, he goes through and describes a design flow that would allow primar...