Blog

  • FPGA camera lane detection with ZYNQ ZC702

    dimiterk
    A couple of months back I received a ZC702 Xilinx development board from Randall after pitching an idea on how to build an embedded vision project. The board arrived a couple of weeks later (thank you Randall) and I started working on the steps to bu...

  • The Art of FPGA Design - Post 34

    fpgaguru
    Sorting Networks - The VHDL implementation of Batcher's sorting algorithm OK, enough with the preliminaries, it's time now for the real deal, how do we implement in an FPGA this parallel sorting network thing. The main design goals are creating ...

  • The Art of FPGA Design - Post 33

    fpgaguru
    Sorting Networks - The Batcher or odd-even mergesort sorting algorithm Now that we have defined the FPGA design engineering problem - parallel sorting of a set of N items in one clock, that is one new sorting operation starting every clock - we ...

  • The Art of FPGA Design - Post 32

    fpgaguru
    Sorting Networks Sorting networks are an interesting and unsolved mathematical puzzle. They are quite different from the usual sorting algorithms one encounters in computer science like bubble sort, quick sort, merge sort, heap sort and so on. W...

  • XXICC (21st Century Co-design) release 0.1a

    johnbeetem
    Here is the new release 0.1a of XXICC.  Rev 0.1a adds the return statement to GCHD (GalaxC for Hardware Design) which allows a hardware module to return a value without using an output port.  Rev 0.1a also adds GCHD comparison operators mis...

  • The Art of FPGA Design - Post 31

    fpgaguru
    Sorting and Searching Algorithms Now that we went through a variety of VHDL design building blocks and we saw the techniques to create both generic, reusable and at the same time efficient (in terms of speed and area) designs, using either behav...

  • The Art of FPGA Design - Post 30

    fpgaguru
    The DSP58 Primitive Xilinx has recently announced a new 7nm FPGA family called Versal. Devices in this family will have an improved version of the UltraScale/UltraScale+ DSP48E2 primitive we just studied in the last posts. The new Versal primiti...

  • The Art of FPGA Design - Post 29

    fpgaguru
    The DSP48 Primitive - Complex multipliers Traditionally a complex multiplication can be decomposed into four real multiplications and two additions:      x+i·y=(a+i·b)(c+i·s)=(a·c−b·s)+i·(a·s+b·c) where     i=√−1 ...

  • The Art of FPGA Design - Post 28

    fpgaguru
    The DSP48 Primitive - Inferring larger multipliers The DSP48E2 primitive contains a signed 27x18 multiplier, any signed multiplier up to this size can be implemented with just one such primitive. If we need larger multipliers we can achieve that...

  • The Art of FPGA Design - Post 27

    fpgaguru
    The DSP48 Primitive - Small Multiplications - Two For the Price of One The DSP48E2 primitive contains a signed 27x18 multiplier, any signed multiplier up to this size can be implemented with just one such primitive. Unsigned multiplications are ...

  • A subtractive music synth fully implemented in FPGA

    mdicosmo
    From:https://thetinysynth.wordpress.com/The Tiny Synth, with its synthesis core measuring only 1.5×1.5mm, is probably the smallest subtractive synthesizer out there. Based on the Artix7 device from the latest Xilinx FPGA family, it provides a total o...

  • The Art of FPGA Design - Post 26

    fpgaguru
    The DSP48 Primitive - Wide XOR Mode The DSP48 primitive can be used for more than just multiply and accumulate. It can for example implement very wide XOR functions. Apart from the obvious ability of XORing two 48-bit operands using the A conca...

  • The Art of FPGA Design - Post 25

    fpgaguru
    The DSP48 Primitive - Symmetric FIR with DSP48 Primitive Instantiations We will now add the option of choosing between DSP48 inference or primitive instantiations to the symmetric FIR introduced in Post 22. It might make sense to review Post 22 ...

  • The Art of FPGA Design - Post 24

    fpgaguru
    The DSP48 Primitive - FIR with DSP48 Primitive Instantiations After a break I will be resuming my weekly posts on The Art of FPGA Design. In the last posts we started looking at the DSP48 primitive, essentially a signed 27x18 multiplier which al...

  • Introducing Ultra96-V2

    bhfletcher
    Yesterday, Avnet announced the Ultra96-V2 as a replacement for the Ultra96 which is going EOL.https://news.avnet.com/press-release/avnet/avnet-introduces-ultra96-v2-development-board  While Ultra96-V2 has the same Xilinx Zynq UltraScale+ MP...

  • LCD panel + FPGA with an HDMI sink = External Display

    avnrdf
    Continuing from where I left off in Driving a Laptop LCD using an FPGA, I moved the 'TMDS to LVDS converter board' to perf board, and soldered the differential pairs from the LCD panel onto it.I used headers (to connect wires) for the connections bet...

  • An FPGA-Based Organ Tuner

    johnbeetem
    Disclaimer: I posted this project hoping that it would be interesting and useful.  However, it is provided "as is" with NO WARRANTY of any kind and if you connect it to an actual organ you must know what you're doing to avoid damage to the organ...

  • XXICC (21st Century Co-design) release 0.1

    johnbeetem
    Here is the new release 0.1 of XXICC.  I was very busy with work and family obligations over the last few years so I wasn't able to keep up with XXICC as I would have liked.  0.1 is a major release since it adds n-bit integers (1-32 bit...

  • Building (and testing) the Cheap and Tiny FPGA board.

    michaelkellett
    Those of you with long memories will remember the first blog about this board:Ultra cheap and Tiny FPGA Board I've built up a couple of boards and got them running some very simple start up software and VHDL.The good news is that there are o...

  • The N64=>HDMI Conversion Project: Part 3

    muddpup64
    This is a continuation of my on going N64 HDMI project. The last post can be found here: The N64=>HDMI Conversion Project: Part 2 I apologize for the delay in my updates. I am a full time college student and my studies always come first. I ho...

  • The Art of FPGA Design - Post 23

    fpgaguru
    The DSP48 Primitive - Instantiating the DSP48 Behavioral inference has many advantages - relatively simple and compact code, works with signed and unsigned operands of any size, hides the intricacies of the DSP48 primitive from the user. It shou...

  • The Art of FPGA Design - Post 22

    fpgaguru
    The DSP48 Primitive - Behavioral Symmetric FIR Inference The DSP48 primitive has an optional preadder function, which can be used to compute things like PCOUT=PCIN+(A+D)*B, which when used for implementing symmetric or anti-symmetric FIRs can re...

  • The Art of FPGA Design - Post 21

    fpgaguru
    The DSP48 Primitive - Behavioral FIR Inference As mentioned earlier, the DSP48 primitive is an essential part of any signal processing FPGA design and in over 90% of cases it's either FIR like sums of products or complex multiplications. For...

  • The Art of FPGA Design - Post 20

    fpgaguru
    The DSP48 Primitive This post will start a longer series dedicated to the DSP48 primitive, a MAC (multiply/accumulate) block which is the workhorse for any kind of signal processing design that requires lots of mathematical operations beyond sim...

  • The Art of FPGA Design - Post 19

    fpgaguru
    Using the Carry-Save Adder, The Constant Coefficient Multiplier Multiplications in Xilinx FPGAs are done using DSP48s, which are primitives that consist of a 25x18 signed multiplier, a 25-bit preadder and a 48-bit postadder/accumulator. In Ultra...