If you have not setup Vitis, you should first go back and visit my last blog where I talk about setting up the build environment.Learning Vitis: 1 Setting up a Virtual Machine Once you are caught up, if you have used SDSoC, or SDACCEL, you can s...
Disable Screen BlankingAssuming that you have seen the previous blogs and are using the Avnet recommended Ubuntu build environment, here is a tip that will increase your productivity!This is another tip that I found useful! If you have a tip yo...
Hi all, Welcome to a new series of blogs that I am putting together. If there is enough interest, I can continue this, so if you have suggestions and I can work it in, I will try to work through some blogs to answer your questions! Fo...
Within the Avnet 'Zed' Community, we spend a lot of time talking about SoC's with hard-core processors. The original ZedBoard started it all with a Zynq-7000 device with ARM A9. We've also done a lot with Zynq UltraScale+ family and ARM A53 (UltraZed...
Avnet has recently published an update to their Zynq & Zynq UltraScale+ MPSOC Systems Guide. With over 15 years of experience building SOMS for Xilinx FPGA and SoC devices, Avnet has helped countless companies get a jump start on their prod...
Hi all, I've seen quite a few recent posts with people seeing USB 2.0 speeds / connectivity when using the MPSoC. I wanted to let you know that after scouring the interwebz, I think I've pooled enough information together to try to help yo...
Avnet has partnered with Adam Taylor to offer three FREE days of training to help you get started with Xilinx Embedded Design! These trainings include a mix of recorded lectures and hands-on labs with the Avnet MiniZed Development Board. The training...
IntroductionThis project is a follow up from the previous project on porting the PYNQ framework to the ZC702 development board.In this article we will show how to leverage the xOpenCV framework in conjunction with the PYNQ framework to implemen...
Hi Everyone, Avnet has just released the PetaLinux 2019.2 BSP for the Ultra96-V2 board: This BSP includes working WiFi and access point to ease configuration for connecting to the user's WLAN. Instructions for this can be found in the...
In this project we will port the PYNQ framework to the ZC702 development board. Introduction The ZC702 is an official development board from Xilinx. This board sports a ZC7020 ZYNQ FPGA SoC. It comes with a number of peripherals including ...
A key feature of Avnet's Ultra96-V2 board is its WiFi and Bluetooth connectivity that is made possible using the on-board ATWILC3000 module from Microchip. This module is IEEE 802.11 b/g/n plus Bluetooth 5 LE and is certified in more than 75 countrie...
The Xilinx Zynq UltraScale+ MPSoC device has an integrated Platform Management Unit or PMU. This PMU's functionality is described in Chapter 6 of Xilinx UG1085, Zynq UltraScale+ Device Technical Reference Manual. The PMU controls many things on the Z...
I wanted to create a quick post explaining a small trick I noticed in the build process that allowed me to efficiently complete a build for Vitis and the Xilinx ZCU104 development platform. I learned that if you abuse a tool, you can still make...
You may know that Avnet provides PetaLinux BSPs and other reference designs for the Xilinx Zynq and Zynq UltraScale+ Zed SOMs (MicroZed, PicoZed, and UltraZed) and development boards (MiniZed and Ultra96), but did you also know that Avnet provides Xi...
Introduction
I have a small Brevia 2Brevia 2 development board from Lattice Semiconductor featuring one of their XP2-family FPGAs. I'm using it to explore, in a very simple, basic kind of way, digital signal generation and processing. ...
Previous blogs:
FPGA: Making WavesFPGA: Waves 2: Simple Sinewave
Introduction
I have a small Brevia 2 development board [1] from Lattice Semiconductor featuring one of their XP2-family FPGAs. I'm using it to explore, in a v...
FPGA is fun and easy to learn. Interfacing of Digilent Cmod S6 FPGA development board with 7 segment display. In this code 7 segment display is directly connected to FPGA but it can also be connected through BCD to 7 segment decoder to minimize the n...
FPGA: Making Waves Introduction I have a small Brevia 2 development board [1] from Lattice Semiconductor featuring one of their XP2-family FPGAs. I'm using it to explore, in a very simple, basic kind of way, digital signal generation an...
Introduction
I have a small Brevia 2 development board [1] from Lattice Semiconductor, with one of their XP2-family FPGAs on it, that I bought from Farnell a while back. Last year I got as far as doing these two blogs before ...
