• How can I choose FPGA?

    Former Member
    Former Member
    Hi, I am Arun. I am a hardware Engineer with 8years experience in in IoT and RF schematic and pcb design. I am new in FPGA design. How can I start my career in FPGA based design? Kindly advice the initial steps.

  • Altera DE0 Nano

    Altera DE0 Nano
    • https://players.brightcove.net/1362235890001/default_default/index.html?videoId=5525972040001
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  • Not-as-expensive FPGA Boards

    I haven't done a poll in a while so I thought it would be fun and instructive to do one about less-expensive FPGA boards. One of the challenges of getting into FPGA design is that the boards are usually a lot more expensive than a Raspberry Pi or a microcontroller…

  • Intel buys Altera for $54 cash. Is this a good thing?

    I noticed this morning on the financial news where Intel has proposed buying Altera for $54 in cash. Does this give FPGA acceptance in the broader world? Is this good or just a little nudge for this area? Let me know what you think. Thanks, Clem

  • Footprint of DE0 NANO FPGA development mainboard?

    Dear all, I have recently got my hands dirty on the Terasic DE0 NANO FPGA development board which will be part of a larger PCB. The FPGA mainboard will be connected through the connectors it has to my custom PCB but there is nowhere I can find a datasheet…

  • How to change FPGA timing with Excel file?

    Hi, I heard that the timing of FPGA signals can be changed via a MS Office Excel file. The timing of the signals could be designed in an Excel file and then, maybe after conversion, uploaded via RS232 or SPI to the FPGA. In this way the timing could be…

  • Difficulties with interfacing external devices using Altera FPGAs

    How can I interface external analog signals (from a potentiometer for example) and display the bits on the user LEDs? Is it also possible to apply fourier transform on these analog signals? I have both Cyclone 10 LP evaluation kit and the DE 10 Nano standard…

  • Nios II programing error on DE0-Nano

    I have a problem with the implementation of Nios II on DE0-Nano board. Unfortunately, Terasic doesn't update the user manual and it dates back to ages. I have found a tutorial to implement Nios on DE boards. The following image is the Nios connections…

  • Altera FPGA & CPLD Power Management Solutions

    Altera FPGA & CPLD Power Management Solutions Texas Instruments works closely with Altera to recommend the best power solutions for a wide variety of end-equipment applications. TI's diverse power management portfolio adequately supports the power requirements…
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    Lancero SGDMA PCI Express IP core with Windows, Linux and QNX device drivers

    Lancero SGDMA PCI Express IP core with Windows, Linux, QNX drivers.
  • PDF

    USB BitJet Lite (Download cable for Altera devices)

    Faster download with quick configuration of Altera devices will shorten your design cycle and allow you to deliver the products in the market at desired time. SLS BitJet Lite will make this possible. Visit http://www.slscorp.com/pages/usbbitjet_lite.php…
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    USB 3.0 Development Board with Cyclone IV FPGA

    SLS recently launched USB 3.0 Development board with Cyclone IV FPGA. Additional peripherals included make the board much more suitable for this age product prototyping. Peripherals include: DDR2 SDRAM, NAND Flash, CFI FLASH, SDRAM, SD Host and many more…
  • PDF

    High-Definition Video Deinterlacing Using FPGAs-wp-01117-hd-video-deinterlacing.pdf

    This white paper explains different deinterlacing techniques and shows how they can be implemented using Altera’s Video and Image Processing Suite of IP. This video design methodology lets designers explore hardware trade-offs when implementing different…
    • wp-01117-hd-video-deinterlacing.pdf
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    Decrease Total System Costs with Cyclone IV Fpga:wp-01113-lowest-system-cost.pdf

    Altera’s new lowest cost, lowest power devices, the Cyclone IV FPGA family, will demonstrate how FPGAs can reduce total system cost
    • wp-01113-lowest-system-cost.pdf
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  • Cheap Entry into FPGA

    There's been quite a lot of talk in the FPGA group about cheap ways to get started so a couple of weeks ago I decided to forsake the professional setup I use for real work and try one of the cheapest routes I could find. The idea was to try something…

  • Getting started with CPLDs – Index

    Maybe you are interested, but do not know the terminology. Please first check out a great slide show at http://www.elektor.com/Uploads/Files/CPLDFPGAprog_1.pdf Here you will find links to all the articles that make up our CPLD for beginners guide. We…

  • FPGA Modular Firmware Skeleton for multiple instruments - Morph-IC-II, YouTube videos.

    I have developed the following design as the framework for the bus interface of USB2 interfaced FPGA based instruments. This firmware in intended to aid the design of instrumentation using the Morph-IC-II module and other fpga systems interfaced to the…

  • FPGA Dev Kits

    So if you have been following my series of post on what a FPGA is and which is better VHDL or Verilog then you should by now be thinking about the next step - actually buying a development kit. In this post I will talk about the three kits I think you…

  • Video Demo: Learn How Dev Kit Utilities Shorten the Design Process

    The video will give you a closer look at the Cyclone III LS FPGA Development Kit, particularly two utilities that accelerate the design cycle. Watch this 10-minute video and: Learn about two easy-to-use, function-rich dev kit utilities, the Board Test…

  • Cheap Cyclone 10

    I've been following the discussions about the VIDOR4000 in the FPGA group. There was a giveaway associated with the Webinar but of course there will be sonme disapointed non-winners. If you want to get into playing with FPGAs one of the cheapest routes…

  • The N64=>HDMI Conversion Project

    This is a continuation of this post: Custom Vivado Parts/Board Creation and this post: Nintendo 64 Schematic I plan on adding to this blog and over time creating a documented progression of the project. For those who did not take the time to go through…

  • Multiplication on FPGA

    FPGA gets its power from the flexibility. The design process can be time-consuming but you can design basically anything. In this project, I will give some examples of the multiplication and flexibility of FPGAs. Multiplication consumes time and sometimes…

  • Introduction to FPGA with Unboxing DE0-NANO P0082

    I have been chosen as a roadtester for DEO-NANO P0082 and my kit has arrived. I decided before going roadtest project, it will be nice to give a heartbeat and step into FPGA world. Before you go reading, I want to say I am not an FPGA expert but I want…

  • Review of the new Terasic flagship: DE10-Standard FPGA-SoC Developing Board

    Hello. I had a great opportunity to test and to review the Terasic new flagship, the DE10-Standard FPGA-SoC board. We will take a look at what this product has to offer, what is its target group and if it is worth its money. …

  • Trigger pulse generation inside FPGA

    Hello, i am facing small problem with FPGA programming. Problem is simple, i have unknown length trigger pulse (1ns-5us) that should start CCD readout. What i need is to be able to make that signal as short as possible, so i don't waste clock cycles to…