Hello everyone,
happy new year. Please guys can you help me to fix my problem. I have programmed a HLS IP for using in vivado to transfer data from PL to PS. I am using pynq overlay. When i start the IP by writing in the register of the custom ip (0x0…
Instantiating the DSPFP32 the Easy Way
The final thing we need to use the new Versal DSPFP32 hardened floating point primitive is a way to access them through VHDL code. While it would be very nice to be able to infer the primitives, especially since…
The New DSPFP32 Primitive in Versal FPGAs
The DSP primitive in the latest Versal FPGA family is called DSP58 and it already has a number of improvements over the latest DSP48 flavors, mainly an increase from 27x18 signed multiplier and 48-bit post adder…
VHDL-2008 FP32 Support in Vivado
VHDL-2008 introduced native support for floating point types with FLOAT, which is an arbitrary precision floating point type. While you can define generic modules with ports of unconstrained FLOAT type, or any actual…
Hello there,
I just posted a video on YouTube about Polyphase filters. You can check it out here:
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Part 2 of a little double post to document the porting of a small FPGA design from a Zynq with ARM + Linux + Pynq + Python to a smaller Spartan with MicroBlaze soft controller + bare metal.
In post 1 , I show the Vivado design differences. Zynq uses…
A little double post to document the porting of a small FPGA design from a Zynq with ARM + Linux + Pynq + Python to a smaller Spartan with MicroBlaze soft controller + bare metal.
The post focuses on the software / firmware aspect. How I migrated…
Continuation of Learning AMD Zynq: a project to generate a set of PWM signals. 2 - add overall control block, delay and pulse signal .
yepe has a goal to create a set of signals for an ultrasone pulse generator.
Status after Post 2
In Post 2,…
Continuation of Learning AMD Zynq: a project to generate a set of PWM signals. 1 - problem statement and possible approach .
yepe has a goal to create a set of signals for an ultrasone pulse generator.
Status after Post 1
In Post 1, we got the…
yepe has to resolve this problem for a project assignment:
Hi Jan Cumps, I hope you don't mind if I ask a question regarding the PYNQ half-bridge PWM driver. I am working on a student project for school and I need to drive a half-bridge for…
Introduction
This is still work in progress - I've only reached the simulation phase and haven't tried it on a device yet - but I thought it might be of some interest.
Back when I did my 'Making Waves' blogs [1], I implemented a fast, unrolled, pipelined…
Introduction
Some more simple DSP [digital signal processing] stuff with my lovely little Lattice Brevia-2 board with its XP2 FPGA.
A couple of years back, I did a collection of blogs called 'Waves' using this board (see the links at the end). For…
Reasons to switch from Spartan-6 to Spartan-7 FPGAs #1
Build a project with the Arty S7 - Line Follower Robot (Part 1) - Introduction
Build a project with the Arty S7 - Line Follower Robot (Part 2) - Setting up Vivado 2019.2 and Demo program…
A quick update on the hardware issue. I tried powering the board and it didn't power up. It turns out the hardware had a short-circuit in production. Short in R220 and R217 had resulted in the failure of a 3.3V supply to the board which was removed. Even…
I started my FPGA journey with VHDL. Hence, I'm quite comfortable with VHDL. I tried learning Verilog, but it seems redundant to me as I already knew one HDL, so I gave up on learning Verilog.
However, while pursuing my master's, I saw that Verilog…
Hello everyone, I'm among the selected challengers for the 7 ways to leave your Spartan-6 design challenge. Firstly I would like to thank the e14 community for providing me with the Arty S7 FPGA board. This will be my first FPGA board, having one of the…
When your design has more than a single clock, you'll have to deal with cross-clock-domain situations. In my search for good online trainings, I bumped on this example from SURF-VHDL: How to compute the frequency of a clock . In this example, you have…
This document is based on “Migrating Spartan-6 Designs to 7 Series & Beyond” document of Adam Taylor. There are a lot of interesting features in the new family and development tools. To describe these differences, I will use two cookies: A spartan 6-based…
When we build the camera block we add the blk_memory and it seems to add it properly:
But after we build the whole design and make a wrapper it seems to us like he does not find the blk_memory:
we glade for some help please, do you know what…
I'm going to try and run an i2c design in VHDL fabric. For self-training. The target device is the Rohm BH1790 optical heart rate sensor. It's a device where the i2c protocol is straightforward but strict. A good candidate for training - a RTL state machine…
I'm going to try out a VHDL driver for the Hitachi HD44780 LCD driver. I've ported it for several microcontrollers (TI Hercules , Maxim MAX32660 ) and a Linux device in the past. I was going to write a VHDL driver, but found a few potential candidates…
The goal of this post is turn a fixed VHDL design into a configurable one. Change a fixed RAM IP into RAM that can be sized, without changing source or logic.
I use michaelkellett 's VHDL RAM Memory design before: use RAM design for Altera Cyclone on…
Introduction
Quick little project to make an egg timer using the MAX II board that I bought over the summer.
Initially, I'll just have it counting down from three minutes. If I feel suitably inspired later, I
might extend it to allow setting the…
Recent Advances in Vivado VHDL-2008 Support
Previous posts in this blog were made in the 2018-2019 period. Some of the issues presented were an attempt to work around VHDL-2008 support limitations in Vivado at that point in time. Since then, significant…
