• Some challenges with FPGAs?

    How does partial reconfiguration in FPGA impact power consumption and performance in real-time applications? Additionally, what are the challenges in implementing high-speed serial communication protocols like PCIe or JESD204B on an FPGA?

  • WiFi SD Card application

    Hi, MicroSD Card : This represents a memory card, typically used for storage. SoC (System on a Chip) : This is the central processing unit, the "brain" of the system. It handles data processing and communication between different components. …

  • Turing my M5stack core2 to a flipper

    Hey guys, Im new to coding, but have general knowledge of hardware. Im about to take on task which is out my scrope but wit chatgpt i will try it. this what i will be doing, i bought all the parts , the hard part is the coding. if anyone is willing to…

  • Using waveshare CANopen interface with zcu102

    Is there any guide or example to use the CANopen interface with zcu102 board. I just want to make the connection and send some data for testing. Thank you

  • Zynq PS Spi and Quad Spi referance design tutorial Help

    I'm trying to make communicate between ps7_spi_0 and axi_quad_spi. This is block diagram. FCLK_CLK0 is 100 Mhz. SPI_0 is 166.666666 Mhz C code : /* * helloworld.c: simple test application * * This application configures UART 16550 to baud…

  • Help Object detection and tracking with color space conversion and morph operators

    Help Object detection and tracking with color space conversion and morph operators I want to implement with boundingbox the opencv example code on the link: https://www.opencv-srf.com/2010/09/object-detection-using-color-seperation.html …

  • How to build Xilinx Default HDL Project for zcu102 in Window?

    Video link: https://studio.youtube.com/video/nSbfVxOD5vk/edit Courtesy to: https://wiki.analog.com/resources/fpga/docs/build Prerequisites: Prerequisites: Vivado installed Steps to build: Cygwin installation https://www.cygwin.com…

  • Affordable Versal parts and their penetration in hobbyist circles

    Good day all, It's been a while since relatively affordable Versal boards came around - at least two sub-$1000 parts from reputable suppliers are available, as well as very interesting board that combines AMD Ryzen with Versal Edge device (that's a…

  • My first step into the FPGA world

    Almost a year ago, I received a very nice surprise from e14. Unfortunately, until now it sat aside, waiting for some love. This is going to change soon! The board The CMOD S7 from Digilent is a very nice little board, fitted with a Spartan 7 FPGA…

  • Booting ZUB1CG with AES-ACC-DPEMMC-G

    Project Purpose: The primary goal of this project is to explore and showcase the capabilities of the AES-ACC-DPEMMC-G module. This includes demonstrating its functionality, explaining its operation, and deploying it in practical scenarios. Although…

  • Does anyone knows how to program the FPGA on Arduino Vidor 4000?

    Hi, I know this question may be asked on Arduino Forum but it could be that someone on elment14 have tried Arduino Vidor 400 and proramed it using the instructions provided on getting started guide for Vidor 4000 https://docs.arduino.cc/tutorials…

  • PYNQ-Z2 Base Overlay Video Modification

    Hello, I have the PYNQ-Z2 board, and using Vivado 2019.2 and PYNQ Image V2.4 I am working on accelerating canny edge detection on PL and then connecting it to PS to do lane detection using hough transform Input is from HDMI-in, output goes to HDMI…

  • PYNQ Z2 FPGA

    Hello Everyone I am Saurav and I am trying to learn PYNQ Z2 FPGA board. I dont know the correct way to reupload python code from Jupyter to Z2 board, Suppose I made some changes in my code and I want to check that code how should I do that The steps…

  • How to use Vitis HLS IP in Python Pynq overlay Environment.

    Hello everyone, happy new year. Please guys can you help me to fix my problem. I have programmed a HLS IP for using in vivado to transfer data from PL to PS. I am using pynq overlay. When i start the IP by writing in the register of the custom ip (0x0…

  • Suggestions for designing with ZYNQ MPSoC UltraScale+ ZCU104: Using PS side DDR4 memory for storing trained weights and biases of Convolutional Neural Network(CNN) for implementation of CNN inference in real-time.

    I have trained weights and biases from a CNN network for different layers. I have converted those data into fixed point 16-bit binary format and saved them as .txt files for different convolutional layers. Since the data files are too large to accommodate…

  • How to Create Adder, LPF and HPF, Amplifier Circuits in FPGA LabVIEW

    Hello, I have NI cRIO 9024 with NI 9215 and NI 9263. I want to design a digital signal processing circuit with the following sequence From Sensor 04 Voltages will be Received at AI0-3 Module > I want to Add These 04 Signals > Amplified Them >…

  • FPGA and DSP ep. 4: Polyphase Filters

    Hello there, I just posted a video on YouTube about Polyphase filters. You can check it out here: You don't have permission to edit metadata of this video. …

  • Blinking a LED with PYNQ in Kria KV260 / KR260

    1. Introduction In this article, we will install PYNQ in Ubuntu 22.04 and then I will show you how to do a simple LED blinking using Python in PYNQ. 2. Installing PYNQ in KV260 The Xilinx/Kria-PYNQ is the main repository for everything related…

  • Booting Ubuntu 22.04 in Kria KV260 (or KR260)

    1. Introduction In the previous article , we looked at how we can upgrade the Kria SOM firmware to make it able to boot Ubuntu 22.04 (without the firmware, it can only boot Ubuntu 20.04). In this article, we will build on that and boot the OS. Booting…

  • Kria (KV260/KR260) firmware update for booting Ubuntu 22.04

    1. Introduction KV260 and KR260 firmware by default cannot boot the Ubuntu 22.04. Therefore, an update to the firmware is necessary. In this article, I will show you how to update the firmware step by step. I have the following setup. Petalinux…

  • Port a VHDL design from AMD Zynq & Pynq to Spartan-7 & MicroBlaze - part 2: software

    Part 2 of a little double post to document the porting of a small FPGA design from a Zynq with ARM + Linux + Pynq + Python to a smaller Spartan with MicroBlaze soft controller + bare metal. In post 1 , I show the Vivado design differences. Zynq uses…

  • Port a VHDL design from AMD Zynq & Pynq to Spartan-7 & MicroBlaze - part 1: hardware

    A little double post to document the porting of a small FPGA design from a Zynq with ARM + Linux + Pynq + Python to a smaller Spartan with MicroBlaze soft controller + bare metal. The post focuses on the software / firmware aspect. How I migrated…
  • Learning AMD Zynq: a project to generate a set of PWM signals. 3 - add GATE signal and demodulation clock

    Learning AMD Zynq: a project to generate a set of PWM signals. 3 - add GATE signal and demodulation clock

    Continuation of Learning AMD Zynq: a project to generate a set of PWM signals. 2 - add overall control block, delay and pulse signal . yepe has a goal to create a set of signals for an ultrasone pulse generator. Status after Post 2 In Post 2,…
  • Learning AMD Zynq: a project to generate a set of PWM signals. 2 - add overall control block, delay and pulse signal

    Learning AMD Zynq: a project to generate a set of PWM signals. 2 - add overall control block, delay and pulse signal

    Continuation of Learning AMD Zynq: a project to generate a set of PWM signals. 1 - problem statement and possible approach . yepe has a goal to create a set of signals for an ultrasone pulse generator. Status after Post 1 In Post 1, we got the…
  • Learning AMD Zynq: a project to generate a set of PWM signals. 1 - problem statement and possible approach

    Learning AMD Zynq: a project to generate a set of PWM signals. 1 - problem statement and possible approach

    yepe has to resolve this problem for a project assignment: Hi Jan Cumps, I hope you don't mind if I ask a question regarding the PYNQ half-bridge PWM driver. I am working on a student project for school and I need to drive a half-bridge for…