I'm trying to make communicate between ps7_spi_0 and axi_quad_spi. This is block diagram. FCLK_CLK0 is 100 Mhz. SPI_0 is 166.666666 Mhz
C code :
/*
* helloworld.c: simple test application
*
* This application configures UART 16550 to baud…
Introduction
This project is part 1 of a 5 part series of projects, where we will progressively create AI enabled platforms for the following Tria development boards:
ZUBoard
Ultra96-V2
UltraZed-7EV
These projects can be rebuilt using the…
You can run Vivado and Vitis on WSL2 . One reason to do that, is that you can run the provided build scripts as is. You 'll be able to recreate the source for the Pynq Base Vivado project, and Digilent's Vivado project for the Arty Z7 (and S7). It 'll…
You can run Vivado and Vitis on WSL2 . One reason to do that, is that you can run the provided build scripts as is. You 'll be able to recreate the source for the Pynq Base Vivado project, and Digilent's Vivado project for the Arty Z7 (and S7). It 'll…
I'm installing the Vitis and Vivado tools on a WSL instance. Most of tutorials on scripting and build automated are for Linux. I want to test this out. My WSL runs Ubuntu 20.04.3 LTS.
I was surprised that WSL actually shows the install GUI. I thought…
In the screen grab I chose the COMPLETE set of files. It's huge, but was worth it considering how many attempts it took to finish a clean installation! Doing a complete installation also seems to eliminate some issues I had with the install wanting to…
Hello,
I have the PYNQ-Z2 board, and using Vivado 2019.2 and PYNQ Image V2.4
I am working on accelerating canny edge detection on PL and then connecting it to PS to do lane detection using hough transform
Input is from HDMI-in, output goes to HDMI…
Hello everyone,
happy new year. Please guys can you help me to fix my problem. I have programmed a HLS IP for using in vivado to transfer data from PL to PS. I am using pynq overlay. When i start the IP by writing in the register of the custom ip (0x0…
Part 2 of a little double post to document the porting of a small FPGA design from a Zynq with ARM + Linux + Pynq + Python to a smaller Spartan with MicroBlaze soft controller + bare metal.
In post 1 , I show the Vivado design differences. Zynq uses…
A little double post to document the porting of a small FPGA design from a Zynq with ARM + Linux + Pynq + Python to a smaller Spartan with MicroBlaze soft controller + bare metal.
The post focuses on the software / firmware aspect. How I migrated…
Continuation of Learning AMD Zynq: a project to generate a set of PWM signals. 2 - add overall control block, delay and pulse signal .
yepe has a goal to create a set of signals for an ultrasone pulse generator.
Status after Post 2
In Post 2,…
Continuation of Learning AMD Zynq: a project to generate a set of PWM signals. 1 - problem statement and possible approach .
yepe has a goal to create a set of signals for an ultrasone pulse generator.
Status after Post 1
In Post 1, we got the…
yepe has to resolve this problem for a project assignment:
Hi Jan Cumps, I hope you don't mind if I ask a question regarding the PYNQ half-bridge PWM driver. I am working on a student project for school and I need to drive a half-bridge for…
Hi,
I am Arun. I am a hardware Engineer with 8years experience in in IoT and RF schematic and pcb design. I am new in FPGA design. How can I start my career in FPGA based design? Kindly advice the initial steps.
Introduction
In the previous blog, FPGA ADSR envelope generator for sound synthesis , we discussed ADSR envelope generators. The data input to the ADSR module was hardcoded. It would be nice to be able to enter the step increments with knobs for each…
ADSR envelope generator for sound synthesis.
In the previous blog we implemented a Direct Digital Frequency Synthesis module (DDFS ) that can generate an unmodulated audio-frequency tone. In this blog we will implement an ADSR (attack-decay-sustain…
DDFS - Direct Digital Frequency Synthesis
DDFS is a digitally-controlled method of generating multiple frequencies from a reference frequency source. DDFS is a method of producing a tunable digital or analog waveform. First the data points of the waveform…
Finishing up with combinational circuit design exercises in System Verilog. This time we are going to do exercises on another representation of numbers, BCD (binary-coded decimal format)
Table of Contents
Binary-coded decimal
1-digit BCD…
We continue with combinational circuit design exercises in SystemVerilog. This time we are going to do exercises on number representation formats using a simplified floating point format.
Table of Contents
Floating point arithmetic
Simplified…
RTL Combinational Circuit - Design Examples - Barrel Shifter RTL Combinational Circuit
We continue experimenting with RTL Combinational Circuits designed in SystemVerilog. In this blog we are going to design circuits around a very useful circuit that…
In the previous chapter we reviewed some of the main SystemVerilog operators that allow us to describe the operation of combinational logic circuits. In this chapter we will review some of the SystemVerilog constructs that allow us to describe parts of…
I continue my series of notes on SystemVerilog as I learn. In this case I dedicate the study notes to Verilog operators as an introduction to combinational circuits. I'll cover always blocks and other routing constructs in a later blog.
Table of Contents…
I am learning SystemVerilog HDL. I started reading the book FPGA Prototyping By SystemVerilog Examples . These are my study notes and what I am learning about SystemVerilog. My idea is to do exercises with the Digilent Arty S7 50 board obtained in the…
Reasons to switch from Spartan-6 to Spartan-7 FPGAs #1
Build a project with the Arty S7 - Line Follower Robot (Part 1) - Introduction
Build a project with the Arty S7 - Line Follower Robot (Part 2) - Setting up Vivado 2019.2 and Demo program…
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