• Setting up CAN interface for Xilinx ZCU102

    I am working on zcu102 ultrascale board. I want to use CAN interface to send and receive data, Is there any guide or tutorial to setup this connection? Are there any drivers needed to be installed separately? (CAN4Linux or SocketCAN) On loopback…

  • Using waveshare CANopen interface with zcu102

    Is there any guide or example to use the CANopen interface with zcu102 board. I just want to make the connection and send some data for testing. Thank you

  • Zynq PS Spi and Quad Spi referance design tutorial Help

    I'm trying to make communicate between ps7_spi_0 and axi_quad_spi. This is block diagram. FCLK_CLK0 is 100 Mhz. SPI_0 is 166.666666 Mhz C code : /* * helloworld.c: simple test application * * This application configures UART 16550 to baud…

  • Vivado, Vitis and PetaLinux on Windows Sublayer for Linux (WSL2): solve xsdb segmentation fault

    You can run Vivado and Vitis on WSL2 . One reason to do that, is that you can run the provided build scripts as is. You 'll be able to recreate the source for the Pynq Base Vivado project, and Digilent's Vivado project for the Arty Z7 (and S7). It 'll…

  • Vivado, Vitis and PetaLinux on Windows Sublayer for Linux (WSL2): connect to the USB debugger as a normal user

    You can run Vivado and Vitis on WSL2 . One reason to do that, is that you can run the provided build scripts as is. You 'll be able to recreate the source for the Pynq Base Vivado project, and Digilent's Vivado project for the Arty Z7 (and S7). It 'll…

  • Vivado, Vitis and PetaLinux on Windows Sublayer for Linux (WSL2): attach and detach your USB debugger

    You can run Vivado and Vitis on WSL2 . One reason to do that, is that you can run the provided build scripts as is. You 'll be able to recreate the source for the Pynq Base Vivado project, and Digilent's Vivado project for the Arty Z7 (and S7). It 'll…

  • How to build Xilinx Default HDL Project for zcu102 in Window?

    Video link: https://studio.youtube.com/video/nSbfVxOD5vk/edit Courtesy to: https://wiki.analog.com/resources/fpga/docs/build Prerequisites: Prerequisites: Vivado installed Steps to build: Cygwin installation https://www.cygwin.com…

  • Affordable Versal parts and their penetration in hobbyist circles

    Good day all, It's been a while since relatively affordable Versal boards came around - at least two sub-$1000 parts from reputable suppliers are available, as well as very interesting board that combines AMD Ryzen with Versal Edge device (that's a…

  • in L3 Corner Track example. Why the flow buffer needs to be created everytime in loop?

    How can i reduce the execution time of "L3 Corner Track example" using my own video. I have observed in Vitis Analyzer that optical flow buffers are created in a loop which are adding more time to the execution process. I already managed to move other…

  • Booting ZUB1CG with AES-ACC-DPEMMC-G

    Project Purpose: The primary goal of this project is to explore and showcase the capabilities of the AES-ACC-DPEMMC-G module. This includes demonstrating its functionality, explaining its operation, and deploying it in practical scenarios. Although…

  • PYNQ Z2 FPGA

    Hello Everyone I am Saurav and I am trying to learn PYNQ Z2 FPGA board. I dont know the correct way to reupload python code from Jupyter to Z2 board, Suppose I made some changes in my code and I want to check that code how should I do that The steps…

  • The Art of FPGA Design - Post 40

    Instantiating the DSPFP32 the Easy Way The final thing we need to use the new Versal DSPFP32 hardened floating point primitive is a way to access them through VHDL code. While it would be very nice to be able to infer the primitives, especially since…

  • The New DSPFP32 Primitive in Versal FPGAs

    The New DSPFP32 Primitive in Versal FPGAs The DSP primitive in the latest Versal FPGA family is called DSP58 and it already has a number of improvements over the latest DSP48 flavors, mainly an increase from 27x18 signed multiplier and 48-bit post adder…

  • The Art of FPGA Design - Post 38

    VHDL-2008 FP32 Support in Vivado VHDL-2008 introduced native support for floating point types with FLOAT, which is an arbitrary precision floating point type. While you can define generic modules with ports of unconstrained FLOAT type, or any actual…

  • Blinking a LED with PYNQ in Kria KV260 / KR260

    1. Introduction In this article, we will install PYNQ in Ubuntu 22.04 and then I will show you how to do a simple LED blinking using Python in PYNQ. 2. Installing PYNQ in KV260 The Xilinx/Kria-PYNQ is the main repository for everything related…

  • Booting Ubuntu 22.04 in Kria KV260 (or KR260)

    1. Introduction In the previous article , we looked at how we can upgrade the Kria SOM firmware to make it able to boot Ubuntu 22.04 (without the firmware, it can only boot Ubuntu 20.04). In this article, we will build on that and boot the OS. Booting…
  • Vitis-AI 3.0 designs for Ultra96-V2 and ZUBoard

    Vitis-AI 3.0 designs for Ultra96-V2 and ZUBoard

    Avnet has just released a series of projects that builds up Vitis-AI 3.0 and ROS2 enabled designs for Ultra96-V2 and ZUBoard. Type Description ZUB1CG Links U96V2 Links Hackster 1 Building the foundational…

  • How can I choose FPGA?

    Former Member
    Former Member
    Hi, I am Arun. I am a hardware Engineer with 8years experience in in IoT and RF schematic and pcb design. I am new in FPGA design. How can I start my career in FPGA based design? Kindly advice the initial steps.

  • Follow Up to the 7 Ways to Leave Your Spartan-6 Program: How Well Do You Like Working with the Spartan-7 FPGA?

    element14's 7 Ways to Leave Your Spartan-6 Program concluded several months ago. Twenty-five members participated in the program. Overall, they produced an incredible number of blogs. It was interesting to read all the comments, too. As an observer, I…

  • Pynq Version 3 released

    Pynq has released version 3 in October. Highlights (from the release notes ): All overlays built with Vivado 2022.1 Linux kernel and build updated to Petalinux 2022.1 Productivity additions - software Updated to Python 3.10 Updated…
  • SystemVerilog Study Notes. Hex-Digit to Seven-Segment LED Decoder RTL Combinational Circuit

    SystemVerilog Study Notes. Hex-Digit to Seven-Segment LED Decoder RTL Combinational Circuit

    RTL Combinational Circuit - Design Examples - Hex-Digit to Seven-Segment LED Decoder RTL Combinational Circuit We have been reviewing the main constructs and operators for designing combinational logic circuits with the SystemVerilog HDL. Let's apply…
  • SystemVerilog Study Notes. RTL Combinational Circuit Operators

    SystemVerilog Study Notes. RTL Combinational Circuit Operators

    I continue my series of notes on SystemVerilog as I learn. In this case I dedicate the study notes to Verilog operators as an introduction to combinational circuits. I'll cover always blocks and other routing constructs in a later blog. Table of Contents…

  • Build a project with the Arty S7 - Line Follower Robot (Part 7) - Summary

    Reasons to switch from Spartan-6 to Spartan-7 FPGAs #1 Build a project with the Arty S7 - Line Follower Robot (Part 1) - Introduction Build a project with the Arty S7 - Line Follower Robot (Part 2) - Setting up Vivado 2019.2 and Demo program…

  • Build a project with the Arty S7 - Line Follower Robot (Part 4) - Hardware Assembly

    Reasons to switch from Spartan-6 to Spartan-7 FPGAs #1 Build a project with the Arty S7 - Line Follower Robot (Part 1) - Introduction Build a project with the Arty S7 - Line Follower Robot (Part 2) - Setting up Vivado 2019.2 and Demo program…

  • RC6 cipher implemented in Verilog

    Hello everyone. I welcome you to this blog post describing my project as part of 7 Ways to Leave Your Spartan-6 FPGA contest. In this blog post I will describe my core project as part of this competition. As part of this competition I originally promised…