Hello.I had a great opportunity to test and to review the Terasic new flagship, the DE10-Standard FPGA-SoC board.We will take a look at what this product has to offer, what is its target group and if it is worth its money.www.youtube.com/watch
The XuLA2 standard runs on a 12 MHz clock. That's plenty for many things, but not enough for some designs.In my PWM with DeadBand project, for instance, the effective signal frequency that the module outputs is halved for each bit of precis...
A PWM module for FPGAs that supports dead band.A VHDL project that generates two opposite PWM signals with a dead band. You can change the duty cycle with a rotary encoder.When you drive half-bridge designs, you need a control signal for both transis...
How to use a rotary encoder with the XuLA2 and the Spartan-6 FPGA.Another real world example: I'm checking if the Xess Rotary Encoder library works with the encoder I use in a GaN half-bridge design.TL;DR: yes it worksXess has a plug-in board with a ...
Let's try to do something real with the Xilinx Spartan-6 FPGA: write a set of data to an SD card. To boost the FPGA skills, I'm refreshing theory and checking out some real designs.For a standalone XuLA2 board, talking to SD cards is a good prac...
I purchased a Xess XuLA2. It arrived this morning.This post is the story of my first steps I have a little bit of experience with FPGAs. I learned digital electronics in the early-to-mid 80's. My VHDL skills are beginner level and I...
This is the summary page for the XXICC (21st Century Co-design) project. XXICC was previously hosted at Google Code, which no longer accepts new projects or edits to existing projects. xxicc.org now links to this page. The latest XXICC rel...
There is quite a number of boards coming to market this year 2016.These include various hats for Raspberry Pi, Beagleboneblack and the like.However I've yet to see a really simple OSH design in Kicad format for any iCE40 chip.If novices and young use...
FPGADuring the 2015 Community Awards, we asked you to take a cursory look into the future and give us your predictions for the new platforms and technologies that are likely to dominate in 2016.Even though it didn't make the initial nominations, Fiel...
Arachne-pnr by Cotton Seed (who also uses pseudonyms cseed and mian2zi3) is an open-source FPGA placement and routing tool for Lattice iCE40 FPGAs. It's a companion to the open-source Project IceStorm by Clifford Wolf and Mathias Lasser, which ...
Project IceStorm, by Clifford Wolf and Mathias Lasser, is an amazing project that has reverse-engineered the Lattice iCE40 FPGA's bitstream so that it's finally possible to write open-source FPGA design tools for a real FPGA. I've b...
Release 0.0q has been replaced by: XXICC (21st Century Co-design) release 0.0r Here is the new release 0.0q of XXICC. 0.0q adds logic capacity to Flavia implementation and allows you to specify pull-up, pull-down, and keeper circuits for ...
Dear All, I am very very new learner of VHDL code. I am interested to learn hoe to read an image by VHDL code. My target is to develop an image edge detector. Thanks
This blog is part 3 of a 4 part series of implementing a gradient filter on an FPGA. If you have not already read the earlier parts see the link below to get up to speed before reading this blog. Additionally the user can catch some of ou...
Hello:) I am Anton.About 3 years ago I discovered the world of embedded programming.First it was simple Arduino, but after few month I realized, that Arduino is too weak for my ambitions:DI grabed DE1 FPGA from Terasic bo...
Update 28 June 2015: XXICC has been updated to XXICC (21st Century Co-design) release 0.0qHere is the release 0.0p of XXICC. There is no rev 0.0o since the letter O looks too much like the digit 0. 0.0p adds a Flavia implementation for t...
There's been quite a lot of talk in the FPGA group about cheap ways to get started so a couple of weeks ago I decided to forsake the professional setup I use for real work and try one of the cheapest routes I could find. The idea was to try...
Maybe you are interested, but do not know the terminology. Please first check out a great slide show at http://www.elektor.com/Uploads/Files/CPLDFPGAprog_1.pdf Here you will find links to all the articles that make up our CPLD for beginners guid...
This blog is part 2 of a 3 part series of implementing a gradient filter on an FPGA. If you have not already read part2 see the link below to get up to speed before reading this blog. Additionally the user can catch some of our previous b...
Here is the new release 0.0n of XXICC, which adds Xilinx Spartan-6 Flavia implementations for the ValentF(x) LOGI-Pi board and LOGI-Bone. XXICC (21st Century Co-design) is a not-for-profit research project which attempts to bring digital hardwar...
The Problem Typical obstacle detection on low cost mobile indoor robots are usually performed using a variety of sensors, namely sonar and infrared sensors. These sensors provide poor information that is only able to detect the presence of a ref...
Here is the new release 0.0m of XXICC. There is no rev 0.0l since lower-case L looks like digit 1. 0.0m is primarily a maintenance release with bug fixes and improvements to usability. In addition, Flavia: the Free Logic Array has a...
Hardware description languages (HDLs) are a category of programming languages that target digital hardware design. These languages provides special features to design sequential logic( the system evolve over time represented by a clock) or combinatio...
Abstract: This ’blog describes using a ValentF(x) LOGI-EDU board to make a 4-digit BCD (binary-coded decimal) counter using LOGI-EDU’s 4-digit seven-segment LED module. I used both LOGI-Pi and LOGI-Bone FPGA boards to implement the BCD counter ...
