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Threads
548 Discussions
Frequently Asked
Sharing vivado projects
Not Answered
over 3 years ago
Vivado and Zynq: TRI-STATE help
Not Answered
over 3 years ago
i2c bus in zynq
Not Answered
over 3 years ago
Issue with blk_memory after design & wrapper
Not Answered
over 3 years ago
How to fix DMA initialization failure?
Not Answered
over 3 years ago
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Discussion
Vivado, Vitis and PetaLinux on Windows Sublayer for Linux (WSL2): attach and detach your USB debugger
1017
views
0
replies
Started
11 months ago
by
Jan Cumps
Not Answered
Get this on the dmesg "macb ff0e0000.ethernet eth0: Could not attach PHY (-19)"
0
1287
views
1
reply
Latest
11 months ago
by
bidrohini
Discussion
Install Vivado, Vitis and PetaLinux on Windows Sublayer for Linux
10973
views
13
replies
Latest
11 months ago
by
Jan Cumps
Discussion
in L3 Corner Track example. Why the flow buffer needs to be created everytime in loop?
286
views
1
reply
Latest
11 months ago
by
phoenixcomm
Discussion
Seeking Feedback on Your Preference for an AMD Kria Workshop
1819
views
14
replies
Latest
over 1 year ago
by
erik__18
Discussion
Development board to test my ASIC
395
views
1
reply
Latest
over 1 year ago
by
vmate
Discussion
Poll - I'm Planning an FPGA program for Fall 2024 - What Are your Preferences?
1709
views
11
replies
Latest
over 1 year ago
by
javagoza
Not Answered
Arty7 FPGA I not see the vauxp2 values they are only Z
0
261
views
0
replies
Started
over 1 year ago
by Former Member
Not Answered
When should I start programming with a board instead of Verilog sources on a processor
0
447
views
1
reply
Latest
over 1 year ago
by
javagoza
Discussion
storing large dataset on pynq z2 ddr memory
262
views
0
replies
Started
over 1 year ago
by
Hudda
Discussion
Are you looking for a Career Opportunity as an FPGA Programmer at AMD?
4209
views
10
replies
Latest
over 1 year ago
by
_david_
Discussion
Does anyone knows how to program the FPGA on Arduino Vidor 4000?
1004
views
4
replies
Latest
over 1 year ago
by
jc2048
Discussion
PYNQ-Z2 Base Overlay Video Modification
375
views
0
replies
Started
over 1 year ago
by
likeastar
Not Answered
PYNQ Z2 FPGA
0
1009
views
4
replies
Latest
over 1 year ago
by
Saurav006
Discussion
How to use Vitis HLS IP in Python Pynq overlay Environment.
942
views
3
replies
Latest
over 1 year ago
by
flyingbean
Not Answered
Suggestions for designing with ZYNQ MPSoC UltraScale+ ZCU104: Using PS side DDR4 memory for storing trained weights and biases of Convolutional Neural Network(CNN) for implementation of CNN inference in real-time.
0
1161
views
3
replies
Latest
over 1 year ago
by
JB58
Not Answered
GIC vs AXI Interrupt Controller
0
10743
views
10
replies
Latest
over 1 year ago
by
valeteBro
Discussion
UltraScale+ use OCM as shared memory between PetaLinux on A53 and Bare metal on R5
4099
views
4
replies
Latest
over 1 year ago
by
minimartian
Not Answered
How to Create Adder, LPF and HPF, Amplifier Circuits in FPGA LabVIEW
0
1647
views
9
replies
Latest
over 1 year ago
by
jc2048
Discussion
FPGA - Vibration Analysis
5203
views
44
replies
Latest
over 1 year ago
by
shabaz
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