Blog

Xilinx ZYNQ - Blog 6 - Creating Custom IP: A PWM Module in Verilog

shabaz

Note: This is part 6 of a series on working with FPGAs and in particular the Xilinx Zynq-7000S Programmable System-on-Chip with ARM Cortex-A9 processing core. For part 1, click here: Xilinx ZYNQ System-on-Chip - Getting to know the MiniZed Board For ...
- 27 Dec 2018
Path to Programmable - SW Lab 0, Lab 1, Lab 2

aspork42

Welcome to the second half!This is the second half of the Zynq training series. The first half covered the "hardware" side of things; meaning the physical FPGA, the AXI Interface, and a fair amount of "TCL" (pronounced "tickle") interface. In the sec...
- 26 Dec 2018
Xilinx ZYNQ - Blog 5 - Advanced eXtensible Interface (AXI) and Using Block RAM

shabaz

Note: This is part 5 of a series on working with FPGAs and in particular the Xilinx Zynq-7000S Programmable System-on-Chip with ARM Cortex-A9 processing core. For part 1, click here: Xilinx ZYNQ System-on-Chip - Getting to know the MiniZed Board For ...
- 24 Dec 2018
[PP-13] The materials for second module

kk99

We have received a materials for second module of Path to Programmable training.Here is agenda for the second module:In my opinion first three chapters from second module covers the same material from first module. These three laboratories cont...
- 23 Dec 2018
Path to Programmable - Blog 7 - Module 2, ZynqSW Labs 0-3

rsc

The structure for the second training module is as follows:Lab 00 was another installation guide, and I already had the required software installed.The Labs 01-03 were overviews of the SDK program and importing hardware information from Vivado. Since...
- 20 Dec 2018
Debugging by means of Logic Analyzer in Vivado

mu.udhay

Hi Friends , In this Post we deal with Important Aspect in every design - "Debugging" .I would like to make this Post more generalized so that it can be applied to what ever Project you are working on it does not matter , for Reference i wi...
- 20 Dec 2018
Path to Programmable Blog 12 - SDK Project Management & Interrupts

avnrdf

Chapter 8 Video - SDK Project Management This video was about project management in Xilinx SDK: workspaces & how to share/export them, how to import C/C++ files and set up repositories. Lab 8 - SDK Project Management The export tool al...
- 20 Dec 2018
Path to Programmable Blog 11 - Booting Zynq-7000

avnrdf

The next set of videos were centered around the Zynq-7000 boot process. In the previous labs, we programmed the PL & PS over JTAG, which requires an external master. Programming a bootloader to the non-volatile memory on the MiniZed allows it to ...
- 20 Dec 2018
SW Module 4

mconners

This lab was mostly more familiarization with the SDK. The lab goals were stated as follows: Add new software applications to SDKUse example code to target the UART in a Hello World applicationApply example project templates, including&nbsp...
- 16 Dec 2018
Path to Programmable Blog 10 - MiniZed does DVI/HDMI

avnrdf

Continuing (off the course of the syllabus) from where Path to Programmable Blog 7 - Trying out a PL-only VGA design left off, I decided to try generating a HDMI/DVI video signal. HDMI/DVI 101 VGA is an analog signal, where different voltag...
- 12 Dec 2018
Path to Programmable Blog 9 - Developing Applications & Debugging in Xilinx SDK

avnrdf

The videos & labs in Path to Programmable Blog 8 - Developing Zynq Software provided a brief intro to the software development workflow using Xilinx SDK. We now move on to the next set of videos which go over creating applications, using the Xili...
- 12 Dec 2018
Path to Programmable Blog 8 - Developing Zynq Software

avnrdf

In Path to Programmable Blog 6 - Hardware Debugging & some more TCL I finished Module 1 of Path the Programmable - Developing Zynq Hardware. Module 1 was centered around designing peripherals in the PL and interfacing them with the PS using Vivad...
- 11 Dec 2018
Controlling LED Brightness by PWM on Minized

mu.udhay

Hi Friends , in the Previous post we have Created our own Custom PWM IP in Vivado and just Integrated it in our Design.In this Post we will run it On Minized Board.In the Next Post , I will show the Debugging Routes we will trace : For these function...
- 11 Dec 2018
SW Modules 0-3 Introduction

mconners

The first few labs in the SW Module are mostly a more in depth look at the SDK product provided with the Vivado Suite. Lab 0 covers installing all the required tools. All of these steps were completed as part of the first set of labs, so there r...
- 9 Dec 2018
Path to Programmable Blog 7 - Trying out a PL-only VGA design

avnrdf

I tried out a couple of things that weren't a part of the Path to Programmable Course Syllabus, but I thought I'd share them:How to setup the clocks for PL-only designs with the MiniZed3-bit VGA output from the MiniZed without a PMOD. Mini...
- 6 Dec 2018
Path to Programmable Blog 6 - Hardware Debugging & some more TCL

avnrdf

In the previous blog post Path to Programmable Blog 5 - Creating Custom IP , we created custom IP which comprised of some HDL code that implemented a PWM controller, which was then connected to the AXI bus as an AXI-4 Lite Slave, allowing the PS to c...
- 6 Dec 2018
Path to Programmable Blog 5 - Creating Custom IP

avnrdf

In Path to Programmable Blog 4 - Adding a PL Peripheral & using PS DMA, we added Block RAM to the PL and connected it to the PS using the AXI interface. We also looked at how we can use DMA to speed up transfers.The Block RAM was added to the PL ...
- 6 Dec 2018
Path to Programmable - Lab 9 (and Done!)

aspork42

About: Through Avnet, Xilinx and Element14, a training program to learn about the Zynq 7000 platform which is System On Chip combining an FPGA with an ARM processor. This comes to the students as complete development board packed with goodies like a ...
- 4 Dec 2018
Lab 9 - Final HW Lab - TCL me some more

mconners

You may remember when we left off, we removed the JTAG interface from our board design, but we left the PWM module and the Logic Analyzer, so the Block Design looked like this: and I said something about next lab we would do some more TCL ...
- 4 Dec 2018
Path to Programmable Blog 4 - Adding a PL Peripheral & using PS DMA

avnrdf

In the preceding posts, we had a quick look at what Zynq-7000 is (Path to Programmable Blog 1 - Getting Started), the workflow (Path to Programmable Blog 2 - Xilinx Tool Flow & Getting Started with Zynq-7000) and we configured a couple of PS peri...
- 1 Dec 2018
Path to Programmable Blog 3 - PS Peripheral Configuration & TCL

avnrdf

Path to Programmable Blog 2 - Xilinx Tool Flow & Getting Started with Zynq-7000 was an introduction to typical Zynq workflow: first configure the hardware (PS & PL) in Vivado, and then export it to Xilinx SDK to work on the software side of t...
- 1 Dec 2018
Path to Programmable Blog 2 - Xilinx Tool Flow & Getting Started with Zynq-7000

avnrdf

HW Chapter 2 video: Xilinx Embedded Tool FlowThe presenter first went over the different Vivado Design Suite editions: WebPACK is free and supports the common Zynq devices that are found on most development boards (7010 and 7020), and the more expens...
- 30 Nov 2018
Path to Programmable Blog 1 - Getting Started

avnrdf

Introduction Path to Programmable is a training course for Programmable SoCs, like the the Xilinx Zynq-7000 All Programmable SoC.As many others have pointed out, this isn't a typical FPGA/HDL course, since the training material focuses less on t...
- 30 Nov 2018
Week 5 Lab 9 The Power of Scripting using Tcl

snidhi

All my previous blogs can be read in detail here Path to Programmable This blog is further continued from Week 5: Done!! Lab 8 A good read of the previous blog 8 is necessary to understand this Lab 9 as they are related in the project context. ...
- 29 Nov 2018
Week 5 Lab8 Hardware Debugging Zynq Designs

snidhi

All my previous blogs can be read in detail here Path to Programmable This blog is further continued from Week 4: Done!! Lab 7 A good read of the previous blog 7 is necessary to understand this Lab 8 as they are related in the project context.&...
- 29 Nov 2018