This blog is continuing on with the rest of hardware labs. Lab 5: Adding a PL Peripheral In this lab, we added our first PL peripheral to the hardware design. We added an AXI BRAM controller which allows the processing system to access the ...
My project will involve routing a video stream through a neural network element and deriving detection, control and display outputs from the Ultra96v2, so I've been looking for examples that will help me learn how to accomplish this. Unfort...
Ina previous lab I learnt scripting using tcl. This lab expands on the concept by teaching me how to do more complex automation using tcl. I used tcl scripting to finalize the hardware project to be used in developing Zynq MPSoC Software. IN this lab...
IP created is tested via simulation as well as in hardware. Embedded designs like Zynq MPSoC requires software to be written to test IP. The LogiCORE IP JTAG-AXI core was added in a previous last lab and the core was customized. It can generate AXI t...
Vivado has large IP catalog which makes it very easy to connect many of the common interfaces to designs. This lab provided step-by-step instructions on how to create custom IP, add it to the IP catalog, and then connect it to a design. The IP that w...
The next element that I need to tackle for my embedded vision project is the creation of accelerated vision processing IP using Vivado HLS and the xfOpenCV function library. That would allow me to create a component that I could include in my d...
With the software labs complete, it was time to move on to hardware. I think it was recommended that we start with software first, but I think hardware first (the path most P2P trainees chose) probably made more sense. In the software labs, we import...
In this lab the BRAM added from the previous lab is used to buffer data going between the PS and PL. A software application that enables the PS DMA engine was used to show the efficiency gains achieved by passing data between the PL-based BRAM ...
In this lab I expanded the block design by extending the memory space with a PL-based Block RAM (BRAM). The BRAM was used to buffer data going between the PS and PL. I learnt how to:• Add a BRAM from the IP Catalog• Connect AXI peripherals to the Zyn...
This lab gave am an introduction to Tool Command Language (TCL) commands that can be run to modify and archive a project. I learnt how to:• Open and close block designs using TCL• Execute simple TCL commands to manipulate IP Integrator block designs•...
The object of this Lab was to learn how to:•Enable and map all default peripherals in IP Integrator• Set the PS clocks for the PS peripherals and the PL• Create and Run C programs It involved enabling and mapping all the PS peripherals nee...
Lab 1: Vivado includes all the required tools for creating new FPGA and SoC designs as well as the Software Development Kit (SDK) for developing software. The Zynq MPSoC Processing System (PS) has a configurable set of built-in peripherals as well as...
IntroductionIn this blog I will go over the Hardware module of the Ultra96-V2 training. I will change my approach slightly compared to my Software posts: instead of going through each lab, I will cover the main concepts I learnt form the lab exercise...
Having completed the 3 Avnet Ultra96 courses in the Path II Programmable training, it's now time to move on to creating a project with what we have learned. I know what I would like to do conceptually but I doubt that I can successfully impleme...
I've completed the hardware & software courses, so now it is time for the last bit - using Petalinux to build Linux for Zynq & accessing hardware from an application. Petalinux Chapter 1 video: Overview, Review of Ultra96...
Lab 8: SDK Project Management Continuing along with the training, Lab 8 walked through archiving the various elements of an SDK project, including the project source files, run/debug configurations, breakpoints, and workspace settings. Most of i...
The development time of applications can be reduced by taking advantage of libraries of reusable code. Xilinx provides libraries that can be built into a BSP as a selectable option. In this lab we I used is the Xilinx Fat File System for demonstratio...
I have now finished all the training content for Path II Programmable! In this series, we are provided an Ultra96 board and a series of training modules focused around three areas - Hardware (the FPGA side), Software (the microprocessor side), a...
The goal of this lab was to learn:• How to enable the interrupt subsystem to allow hardware interrupts to interrupt software execution• Create an interrupt service routine to handle the hardware interrupt An interrupt handler, also known as an I...
In this series, we are provided an Ultra96 board and a series of training modules focused around three areas - Hardware (the FPGA side), Software (the microprocessor side), and Petalinux (the OS side). In this blog post, I'll outline the Softwar...
In this lab you are advised not to share or archive your workspace simply by zipping it up and sending it off. In my FPGA designs at work the verilog designs are foten shared among two engineers while the software for the SOC FPGa desing is done by o...
