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  • Path II Programmable Week 4 - Completing the Coursework

    ralphjy
    ralphjy
    Week 4 involved finishing up the PetaLinux labs and getting prepared for the post training project. I received the Click Mezzanine Stater kit https://www.newark.com/avnet/aes-acc-u96-me-sk/aes-acc-u96-me-sk-rohs-compliant/dp/03AH7038?st=ultra96%...
    • 7 Nov 2019
  • Developing Zynq UltraScale+ MPSoC Software with Xilinx SDK Lab 7

    buffteethr
    buffteethr
    With the FSBL and PMU firmware done in Lab 06, Lab 07 involved learning how to create a boot image and boot one of my applications from non-volatile memory. A complete boot-up typically of the Zynq requires four things: 1. FSBL2. PMU Firmware3. ...
    • 6 Nov 2019
  • PIIP - PL and Software lessons 0-5 - And a new bit of kit!

    aspork42
    aspork42
    Today, I was able to get a lot of progress with the SW lessons 0-5In this series, we are provided an Ultra96 board and a series of training modules focused around three areas - Hardware (the FPGA side), Software (the microprocessor side), and Petalin...
    • 5 Nov 2019
  • PIIP - HW Lab 09 - Finishing up the HW Series

    aspork42
    aspork42
    Today I finished up the Hardware series with Lab 09 - TCL ScriptingIn this series, we are provided an Ultra96 board and a series of training modules focused around three areas - Hardware (the FPGA side), Software (the microprocessor side), and Petali...
    • 4 Nov 2019
  • Path II Programmable Week 3

    ralphjy
    ralphjy
    Week 3 marks my start of the PetaLinux course.  Before I did that I needed to move the Xilinx development environment to another more powerful computer.  I now consider it somewhat of a miracle that I was able to get through the HW and SW c...
    • 4 Nov 2019
  • PIIP - HW post #3 - Labs 6,7 8. PWM and BRAM tests; Logic Analyzer

    aspork42
    aspork42
    I think post, I will discuss the latest set of labs in the Path II Programmable series.In this series, we are provided an Ultra96 board and a series of training modules focused around three areas - Hardware (the FPGA side), Software (the microprocess...
    • 4 Nov 2019
  • Completed Developing Zynq UltraScale+ MPSoC Software with Xilinx SDK Lab 6

    buffteethr
    buffteethr
    In Lab 5, I learnt how to use the SDK JTAG connection and a TCL script to initialize the ARM processor registers and debug applications. However, in this lab initialization of the ARM processor was done in an embedded fashion using code called the Fi...
    • 3 Nov 2019
  • Path II Programmable Blog 7 - Completing Zynq UltraScale+ MPSoC Software with Xilinx SDK

    avnrdf
    avnrdf
    This blog post completes the Zynq MPSoC software training, most of which has been covered in Path II Programmable Blog 5 - Starting with Zynq UltraScale+ MPSoC Software with Xilinx SDK  and Path II Programmable Blog 6 - More Zynq UltraScale+ MPS...
    • 3 Nov 2019
  • Path II Programmable Blog 6 - More Zynq UltraScale+ MPSoC Software with Xilinx SDK

    avnrdf
    avnrdf
    Continuing from Path II Programmable Blog 5 - Starting with Zynq UltraScale+ MPSoC Software with Xilinx SDK with software lectures/labs 5,6,7 & 8: SW Chapter 5 video: Connecting Hardware & Debugging An overview of the hardware on th...
    • 3 Nov 2019
  • Path II Programmable Blog 5 - Starting with Zynq UltraScale+ MPSoC Software with Xilinx SDK

    avnrdf
    avnrdf
    In Path II Programmable Blog 4 - Finishing off with Zynq UltraScale+ MPSoC Hardware, I completed the hardware courses. Now, it's time for the 'Developing Zynq MPSoC Software Lectures'. SW Chapter 1 video: Zynq MPSoC System Architectu...
    • 3 Nov 2019
  • Week #3

    cmelement14
    cmelement14
    SW Lab 6 - Zynq UltraScale+ MPSoC Boot Process SW Lab 7 - The Release Version of Test_Peripheral Application Doesn't Work. SW Lab 8 - Import & Export SDK Workspace Content SW Lab 9 - LED Light Control SW Lab 10 - File System Library SW...
    • 3 Nov 2019
  • P2P: WiFi Driver issue

    ralphjy
    ralphjy
    I ran into a problem when I was first doing the Ultra96 hardware quickstart where I could not reliably connect my iPad to the Ultra96 WiFi access point.  At that time I just bypassed it by configuring as a WiFi client. Now I have that same ...
    • 2 Nov 2019
  • Path II Programmable Week 2 SW Course

    ralphjy
    ralphjy
    Continuing my week2 post......  this will cover the SW introductory course The objectives for the introductory Software course are:Introduce developers to Xilinx SDK (Software Development Kit)Demonstrate SDK capabilitiesConnect SDK to hardw...
    • 2 Nov 2019
  • Do Not Hide the Problem - A Correct SW Lab 7 Solution

    cmelement14
    cmelement14
    SW Lab 7 Problem Description A Correct SW Lab 7 Solution   SW Lab 7 Problem Description Like other people reported here and there, I noticed the same problem in Experiment 2, SW Lab 7: the peripheral test application stuck at the p...
    • 2 Nov 2019
  • Hello World (Intro, Setup, HW Labs 1 + 2)

    ianrj
    ianrj
    We are now 2 and half weeks into this challenge and I have finally got my Ultra96-V2 printing out Hello World onto the UART. This feels like a suitable point to write my first ever blog post!  Intro to courseThis will be a series of blog po...
    • 30 Oct 2019
  • P2P Week 2: SW Labs 4-8 and 10

    vladrumyan
    vladrumyan
    At this stage I have gone through all the material in the Software course. It does not feel complete though as labs 9 and 11 require some additional hardware which I don’t have yet. I will not cover these two labs in this blog since I am still hoping...
    • 30 Oct 2019
  • Completed Developing Zynq UltraScale+ MPSoC Software with Xilinx SDK Lab 5

    buffteethr
    buffteethr
    Lab 5 is titled Connecting SDK to Hardware. This is the first time I have had to use the dev. board since starting the Software labs. The objectives are to learn how to: Setup the dev. board for operationProgram a bitstream into the PLConfigure ...
    • 29 Oct 2019
  • Path II Programmable Blog 4 - Finishing off with Zynq UltraScale+ MPSoC Hardware

    avnrdf
    avnrdf
    Path II Programmable Blog 3 - More Zynq UltraScale+ MPSoC Hardware covered videos & labs 5, 6, 7 & 8.Moving forward.  HW Chapter 9 video: Tcl Scripting The advantages of Tcl scripting which include sharing projects (since the s...
    • 29 Oct 2019
  • PIIP - HW Lesson 3, 4 and 5

    aspork42
    aspork42
    In this post, I will briefly cover the hardware labs 3, 4, and 5 for Path II Programmable. Lab 3 - Memory and peripherals testThis lab walked through manually adding peripherals like SD interfaces, I2C, SPI, UART, GPIO, and Display Port. The tra...
    • 29 Oct 2019
  • Hackster.IO Ultra96 Technical Training Courses

    ralphjy
    ralphjy
    I saw that hackster.io is offering the Avnet Ultra96 Technical Training Courses as a bundle for a reduced price.  This includes the 3 introductory courses that are used for Path II Programmable plus 3 advanced courses.  Of course, you need ...
    • 28 Oct 2019
  • Path II Programmable Blog 3 - More Zynq UltraScale+ MPSoC Hardware

    avnrdf
    avnrdf
    This blog covers the next set of Zynq HW videos, some of which I have already blogged about at Path II Programmable Blog 2 - An Introduction to Zynq UltraScale+ MPSoC Hardware On the whole, this training material is the same as Path to Programmable v...
    • 28 Oct 2019
  • Path II Programmable Blog 2 - An Introduction to Zynq UltraScale+ MPSoC Hardware

    avnrdf
    avnrdf
    Developing Zynq MPSoC Hardware I decided to start with the Zynq MPSoC Hardware courses - most of it seemed very similar to Zynq-7000 which was covered in Path to Programmable, so I'm hoping that I will be able to get through all of the mater...
    • 28 Oct 2019
  • Path II Programmable Week 2

    ralphjy
    ralphjy
    This week has been more productive than the last since much of the first week was spent configuring the development infrastructure.  I have completed the 10 HW videos (lectures) and the 9 HW labs and the 12 SW videos and 11 SW labs.  I use ...
    • 28 Oct 2019
  • P2P: SW Lab 7 Road Block

    nerdyupdates
    nerdyupdates
    Creating an SD Boot Image This lab was very straightforward, but I ran into an issue that left me scratching my head for a while. This lab used the previously created "Test_Peripherals" application to build the SD card boot image....
    • 27 Oct 2019
  • Path II Programmable Blog 1 - Getting Started

    avnrdf
    avnrdf
    Path II Programmable - An Introduction Continuing from where Path to Programmable left us with Zynq-7000 training, it's time to explore Zynq UltraScale+ MPSoC with Path II Programmable!Zynq UltraScale+ MPSoC follows in the footsteps of Zynq-...
    • 27 Oct 2019
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