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FPGA discusses the latest trends in programmable logic devices, and offers access to education, workshops, webinars on FPGAs, SoCs, and other programmable devices.

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Path to Programmable III
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Path III is the third session in the element14 Community’s structured FPGA-based SoC training. The first Path was held in 2018 and focused on programmable logic devices PLDs and featured the AVNET MiniZed development board, based on AMD’s Zynq-7000 SoC.

Path II convened in 2019 and offered more advanced learning opportunities and featured the AVNET Ultra96-V2 development board, based on AMD’s Zynq UltraScale+ MPSoC.

Path III will double the fun by offering structured training on both the MiniZed and Ultra96-V2 boards. Each training track will be followed by a design/build phase.

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Recent Blogs

  • The Art of FPGA Design - Post 40

    fpgaguru
    Instantiating the DSPFP32 the Easy Way The final thing we need to use the new Versal DSPFP32 hardened floating point primitive is a way to access them through VHDL code. While it would be very nice to be able to infer the primitives, especially since…

  • The New DSPFP32 Primitive in Versal FPGAs

    fpgaguru
    The New DSPFP32 Primitive in Versal FPGAs The DSP primitive in the latest Versal FPGA family is called DSP58 and it already has a number of improvements over the latest DSP48 flavors, mainly an increase from 27x18 signed multiplier and 48-bit post ad…

  • The Art of FPGA Design - Post 38

    fpgaguru
    VHDL-2008 FP32 Support in Vivado VHDL-2008 introduced native support for floating point types with FLOAT, which is an arbitrary precision floating point type. While you can define generic modules with ports of unconstrained FLOAT type, or any actual …

  • Direct Fourier Conversion Software Defined Transceiver

    ad0es
    Decided to expand on my last project: dfcSDR Problem of the moment: This board just isn't gonna work out. Moving to a Kintex 7 board: Software Defined Transceiver Redux ============================================================ Ordered this board…

  • Direct Fourier Conversion Software Defined Radio using Cuda Processing

    ad0es
    This blog will document my effort to make an SDR receiver using an Artix-7 FPGA reading multiple ADCs and sending the raw 16 bit samples over PCIe. Problem of the moment: Too many projects ... not enough time! =======================================…
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